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Method of Fabrication of Strained-SiGe Vertical Transistor

IP.com Disclosure Number: IPCOM000237153D
Publication Date: 2014-Jun-05
Document File: 6 page(s) / 126K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method of forming a strained semiconductor in a vertical transistor architecture.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 56% of the total text.

Page 01 of 6

Method of Fabrication of Strained -

options for future generations of Logic devices and have been in production for memory cells. Strain engineering is mandatory for Silicon (Si) devices to boost the performance and is extremely challenging for vertical transistors. With common strain-engineering methods such as pseudomorphic growth, a material with a different lattice than Si fails due to strain relaxation on the sidewalls and minimal strain along the growth direction ,

which is the same direction as the current flow. Moreover, strain induction by liners is very challenging for vertical structures.

The novel contribution is a method of forming a strained semiconductor in a vertical transistor architecture. Following the formation of the channel plates or pillars , bottom source drain (S/D) regions are formed. Using a two-spacer process, a gate last process is proposed. After opening the gate, while protecting the upper S/D region, Germanium (Ge) is selectively grown on the channel and is driven in o-form strained SiGe semiconductor. The solution is not limited to the SiGe/Si system, but is applicable to any core shell materials or core shell materials that can be thermally mixed .

The following figures represent the process for implementing the method of forming a strained semiconductor in a vertical transistor architecture in a preferred embodiment .

Figure 1: Trench Definition using Hard Mask (HM) Deposition

Figure 2: Trench etch

Figure 3: Oxide Spacer Deposi...