Browse Prior Art Database

Dynamic Test Clock Configuration Using a Shadow Chain Mechanism

IP.com Disclosure Number: IPCOM000237154D
Publication Date: 2014-Jun-05
Document File: 3 page(s) / 210K

Publishing Venue

The IP.com Prior Art Database

Abstract

This document describes an architecture for “Dynamic Test Clock Configuration using a shadow chain mechanism” that helps improving Automatic Test Pattern Generator (ATPG) tool efficiency for designs with scan compression, resulting in a pattern count reduction. The design proposed here resolves limitations seen with commonly used on chip clock control logic programming methods. This solution can be used for any type of design where the problem statement applies. The problem statement, motivation and the concept of the solution are outlined in this document.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Dynamic Test Clock Configuration Using a Shadow Chain Mechanism

Introduction

This document describes an architecture for “Dynamic Test Clock Configuration using a shadow chain mechanism” that helps improving Automatic Test Pattern Generator (ATPG) tool efficiency for designs with scan compression, resulting in a pattern count reduction.  The design proposed here resolves limitations seen with commonly used on chip clock control logic programming methods.

This solution can be used for any type of design where the problem statement applies. The problem statement, motivation and the concept of the solution are outlined in this document.

Problem Statement

A major contributor in the cost vs. lifetime revenue equation of a System on Chip (SOC) is the cost of testing a part. This cost is directly governed by the time taken to test the part.  The higher the test cost of a part, the lower the profit on the chip. Test cost is governed by the time taken to test a part; and this test time depends on –

Currently we perform testing at the highest possible frequency that the design/tester supports. The number of patterns on the other hand is a completely different story; this number depends on many factors:

®    Design size and complexity of logic - architecture, number of clock domains, number of partitions, multi-cycle or false paths in designs, timing complexities etc……

®    ATPG tool efficiency – Governed by complexity of logic, controllability and observability, scan compression factor, patterns generation mechanism, constraints placed on tool etc…..

®    Coverage targets.

Coverage targets, design size, and logic complexity cannot be controlled. But we can control scan compression, controllability and observability, pattern generation mechanism, constraints placed on tool, number of logical partitions, etc…. and we try to optimize them (designs generally have Embedded Deterministic Test (EDT) logic with high scan compression and we insert control and observe/control points to improve coverage). The field that has remained largely un-attended is the mechanism by which we control and configure on-chip test clocks shaper and controller circuit in scan mode.

For configuring test clock using on-chip clock sharper during scan at present we have three approaches:

(1)  Test Points – This approach requires constraints to be placed on ATPG tool to control the Test Point and program them for desired test clock propagation and control. Since these test points are in chain on EDT, placing constraints on them impact results in an increase in pattern count due to compression.

(2)  Dedicated Chain placed outside EDT –This approach overcomes the above described problem since these flops are not on compressed chains (are outside EDT). But this requires pad to be dedicated solely for such a chain. In a designs which has large number of pads available for use during scan test dedicating a pad for this...