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A Method for Inserting Local Loop Type Redundancy in VLSI Layouts

IP.com Disclosure Number: IPCOM000237259D
Publication Date: 2014-Jun-10
Document File: 4 page(s) / 216K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is disclosed for inserting local loop type redundancy in Very Large Scale Integration (VLSI) layouts.

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A Method for Inserting Local Loop Type Redundancy in VLSI Layouts

Disclosed is a method for inserting local loop type redundancy in Very Large Scale Integration (VLSI) layouts.

The method utilizes a template based approach, wherein a set of fixed templates of varying sizes and orientations is used. The method then tests each template against a blockage map and a first template that does not create a conflict for each via is inserted in a layout. A corresponding command is written in C++ language.

In an exemplary scenario, a test fits 12 templates to each via as 2x2, 3x2, 2x3 in each quadrant which refers to 12 templates, 3 via layers and 36 small models.

In a scenario, a greedy approach is utilized that tries each template one at a time for a fit over each via and compares the template's footprint to the blockage map built from layout as shown in fig. 1(a) and fig. 1(b).

Figure 1(a)

Figure 1(b)

The method includes a step of finding size of a macro by calculating a bounding box and allocating blockage maps, such as, an owner map, a via map, a viaabove map and a viabelow map. Here, the owner map is a three dimensional map with location -1 or a

wire number. The via map is boolean with a Vx that represents a layer that is redundant at location -1. The viaabove and viabelow are also boolean, where there is a Vx-1 or

1


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Vx+1 at or near the location wherein, Vx-1 and Vx+1 are not strictly gridded.

The method includes a step of traversing a hierarchy and building interval trees for all horizontal and all vertical wires. For vertical wires, a tree is indexed by X centerline. Each X entry contains a tree that is indexed by a lower Y value, and holds the upper Y value.

After traversing the hierarchy and building the interval trees, the interval trees are

converted into blockage, and are assigned wire numbers. Each unioned wire includes a unique value interval tree and some state logic that makes a process of combining simple. The unique value interval tree and the state logic enable placing of a template over existing metal that is...