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A Method to detect Mask Misalignment in Multi Patterning

IP.com Disclosure Number: IPCOM000237260D
Publication Date: 2014-Jun-10
Document File: 5 page(s) / 78K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to detect mask misalignment in multi-patterning. The method uses a small structure placed on each product die that can detect an error if the width variations in wires due to multi-patterning are beyond a certain threshold.

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Page 01 of 5

A Method to detect Mask Misalignment in Multi Patterning

Current best practices for measuring wiring variability involve placing wiring structures in the kerf of the chip. These structures are necessarily large to get the needed sensitivity and are not routinely tested. Typical structures are "combs and serpentines". These structures cannot be used for diagnostics after the chip is packaged because of placement in the dicing channel (i.e., turn to sawdust). Often, a sample of these structures are tested during wafer manufacturing to determine if a wafer has met the

wafer acceptance criteria (WAC) limits of the manufacturing process. This sampling relies on statistics rather than independent verification of each die.

The disclosed solution is a small structure that can be placed on each product die. It can be used in a go/no-go test or it can be used as a diagnostic structure during the debug process. It can be tested with low cost logic test fixtures. In a go/no-go scenario, the design team can check each die for wire variability criteria. The "check to" criteria can be other than the WAC limits and be programmable by die based on the results of other tests. For example, if the silicon process is "fast", then one set of criteria can be used; if the silicon is "slow", then different criteria can be used. Other parameters can be used to come up with a set of criteria. It is very common that a design team designs to a set of process assumptions that are narrower than the WAC criteria. Traditional wire monitor structures have been considered too large to include in every die; therefore there is a need to create a wire monitoring structure which is area efficient, can be included in each die, can be tested to arbitrary limits and can be tested using low cost logic test structures.

In a diagnostic mode, wire characteristics can be measured "as built" using the new approach for placing this small structure on each product die. Potentially, these measured parameters can be used in a simulation to help debug a failing chip.

The on chip hardware detection circuit flags an error if the width variations in wires due to multi-patterning are beyond a certain threshold. End-to-end dummy wires corresponding to various masks and various metal layers are fabricated on a chip. (Figure 1) The wire width variability can be due to variety of reasons as previously mentioned. It does not matter which factor has finally led to the variation. In some cases, variations with a co-relation may mutually cancel. In other cases, since many are independent, some may not have any contribution while others have a major contribution. Finally, the width dimensions of the wire at a particular level need to meet the specification; otherwise, it leads to failure of the chip due to unaccounted variations.

Figure 1: End-to-end dummy wires corresponding to various masks and various metal layers fabricated on a chip

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Different values of wire widths lead to di...