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Method and structure for dual silicide contacts (NiSi and TiSi)

IP.com Disclosure Number: IPCOM000237286D
Publication Date: 2014-Jun-11
Document File: 5 page(s) / 170K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a structure and integration method for Titanium silicide (TiSi) for negative Field Effect Transistor (nFET) contacts and Nickel/Platinum (Ni/Pt) positive Field Effect Transistor (pFET) contacts.

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Method and structure for dual silicide contacts (

Titanium silicide (TiSi) can be used as a contact material for contact formation because it has a lower contact resistance to negative Field Effect Transistor (nFET) than Nickel/Platinum (Ni/Pt) does. TiSi for positive Field Effect Transistor (pFET) contact has the disadvantage of the Schottky barrier height (i.e., TiSi in nFET contact metal, very high contact resistance for pFET). Ni/Pt with silicide is good for pFET (i.e. band structure), but has disadvantages for nFET due higher contact resistance there .

The novel contribution is a structure and integration method for TiSi for nFET contacts and Ni/Pt pFET contacts.

Figure 1: Starting structure: Device with source/drain (SD) regions exposed, can be planar or three-dimensional (3D0 device (fins)

Figure 2: Mask and open nFET region

Figure 3:Process with nFET (i.e., Si:P) source/drain epitaxy

((NiSi and TiSi

NiSi and TiSi )

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Figure 4: Deposit Titanium

Figure 5: Form Titanium silicide (salicide anneal ~800 C, much higher temperature than NiSi, would relax Silicon Germanium (SiGe))

Figure 6: Strip unreacted Titanium

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Figure 7: Mask nFET, open pFET region

Figure 8: Process with pFET (i.e. SiGe:B) source/drain epitaxy

Figure 9: Deposit Ni/Pt

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Figure 10: Form Nickel silicide (salicide anneal ~400-450C C)

Figure 11: Strip unreacted Ni/Pt, continue with process on record (POR) Middle-of-Line (MOL) processing

Figure 12: Final st...