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Method and System for Increasing Data Bus Performance by Leveraging Existing Error Correction Mechanisms

IP.com Disclosure Number: IPCOM000237348D
Publication Date: 2014-Jun-13
Document File: 5 page(s) / 292K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method and system for increasing data bus performance by leveraging existing error correction mechanisms to transfer data between two interconnected devices.

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Method and System for Increasing Data Bus Performance by Leveraging Existing Error Correction Mechanisms

Disclosed is a method and system for increasing data bus performance by leveraging existing error correction mechanisms when transferring data between two interconnected devices. Here, the system uses characteristics of flash memory, specifically the requirement for strong error correction and the requirement for pseudorandom statistical properties in stored data, to increase data bus performance between a Flash memory controller and its connected Flash memory devices.

FIG. 1, below, illustrates an exemplary configuration of two Flash memory devices connected to a Flash memory controller via a shared data bus. An ECC encoder and an ECC decoder are explicitly shown as part of the Flash memory controller. Since Flash memory (particularly NAND Flash memory) is a lossy storage medium, any controller designed for use with Flash memory must perform error correction in order to reliably read data that was previously written to Flash. Furthermore, modern Flash memory devices impose a requirement that stored data exhibit approximately random statistical properties - bits stored within the Flash memory devices should appear to be uncorrelated with respect to one another and should also exhibit a roughly equal distribution of 0 and 1 values. Because of these two requirements - error correction and randomness - all modern Flash memory controllers implement some form of error correction logic, and also some form of data scrambler. The latter of these, the data scrambler, simply perturbs the data in a reversible fashion using a pseudorandom scrambling sequence.

FIG. 1

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Figure 2, shown below, illustrates a graphical waveform obtained as part of a signal integrity analysis for a particular data bus between a Flash memory controller and one or more connected Flash memory devices. It is common to perform signal integrity analysis under assumptions of worst-case pathological data patterns. These pathological data patterns are chosen to exacerbate specific undesirable bus characteristics such as cross-talk, overshoot, undershoot, ground bounce, and the like. Traditional signal integrity analysis will indicate whether or not worst-case bus conditions will result in an unacceptable error rate for the desired level of system reliability. For a consumer grade product, such as a USB Flash drive, a system designer may tolerate a relatively high bus error rate. For an enterprise-grade storage device, a much higher level of reliability is required. In an attempt to make the worst-case signal look "good enough" (low enough probability of error), a designer will typically resort to techniques such as slowing the bus data rate, adding power-consuming termination resistors, or reducing the number of bus loads. While these techniques can improve reliability, they do so at the cost of reduced performance, increased power consumption, or reduced s...