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Delay configurable standard cell architectures with consistent footprints

IP.com Disclosure Number: IPCOM000237374D
Publication Date: 2014-Jun-16

Publishing Venue

The IP.com Prior Art Database

Abstract

Standard cell designing has been a prime activity in achieving the desired outcome from a technology. There has been a lot of innovation around the cell structures that has provided stability yet flexibility in cell usage for complex microcontrollers. This paper will presents yet another enhancement to standard cell designing that adds flexibility in the design closure. The proposed cell architecture is a modification to existing standard cell architecture that provides the same cell functionality but with delay re-configurability to achieve different delay requirements without having to change the cell footprint. The proposed cell has the following advantages, - It can be used for timing ECO’s without any cell addition. - No change in placement and routing. - Minimize last stage challenges to avoid placement density increase, routing changes, etc.

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Delay configurable standard cell architectures with consistent footprints

Standard cell designing has been a prime activity in achieving the desired outcome from a technology. There has been a lot of innovation around the cell structures that has provided stability yet flexibility in cell usage for complex microcontrollers. This paper will presents yet another enhancement to standard cell designing that adds flexibility in the design closure.

The proposed cell architecture is a modification to existing standard cell architecture that provides the same cell functionality but with delay re-configurability to achieve different delay requirements without having to change the cell footprint.  The proposed cell has the following advantages,

       - It can be used for timing ECO’s without any cell addition.

       - No change in placement and routing.

       - Minimize last stage challenges to avoid placement density increase, routing changes, etc.

Figure 1 shows a transistor level cell design and its corresponding layout.

 Every such design can be seen as divided in 2 units, functional unit and the drive unit, as shown in Figure 2.

Delay Configurable Standard Cell Architecture with Consistent Footprints

The idea of modeling cell as 2 unified stages allows for flexibility in using its driving cell portion as an distinct cell for multiple purposes.  The possible configurations are,

Configuration 1: Detaching the (drive strength) fingers to provide a low order of drive strength;

Configuration 2: Using fingers capacitance at the input to increase cells input pin load, thereby further increasing the delay of the cell;

Configuration 3: Splitting the cell with its fingers so that the fingers can be used by another cell that needs extra drive;

Configuration 4: Using the detached fingers as a buffer to meet DRV; and

Configuration 5: On the same concept, adjusting the setup/hold time of a flop.

 Configuration 1: Detaching the Fingers for low drive strength

In this configuration the metal only portion that is available at the top metal layer can be played to get varied derive strength. It would be beneficial in gaining some extra delay out of the cell and meeting hold violations in the design.  It also will avoid any extra cell addition for meeting hold violations.

Figure 3 shows the details for achieving this configuration.

Configura...