Browse Prior Art Database

Reuse of DFT Patterns in Board-Level Debug

IP.com Disclosure Number: IPCOM000237376D
Publication Date: 2014-Jun-16
Document File: 4 page(s) / 256K

Publishing Venue

The IP.com Prior Art Database

Abstract

This paper describe a design-for-debug method to diagnosis chip on board level with DFT(Design-For-Test) scan patterns that are totally re-used from patterns on Auto Test Equipment (ATE). The combination of hardware and software in this method can reuse original ATPG (Automatic Test Pattern Generation) patterns under multiple scan chains, in addition to the capability of new pattern generation.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Reuse of DFT Patterns in Board-Level Debug

Abstract – This paper describe a design-for-debug method to diagnosis chip on board level with DFT(Design-For-Test) scan patterns that are totally re-used from patterns on Auto Test Equipment (ATE). The combination of hardware and software in this method can reuse original ATPG (Automatic Test Pattern Generation) patterns under multiple scan chains, in addition to the capability of new pattern generation.

When a chip is soldered on a board and undergoes stress testing from the real environment, sometimes the chip does not output desired functional results.  It is helpful to have a debug method that does not require removing the chip from board, especially debugging from ATPG (Automatic Test Pattern Generation) point of view.

In addition to tester debug, we want to duplicate original scan pattern debug on board level.  This can reduce collaborative efforts between DFT engineer and test engineers. This method requires only one round of ATPG, and only one set of patterns for debug both on tester and application board.

On an evaluation board or system, board level debug pins require the JTAG pins only.

The design-spec registers are the extensible parts of IEEE Std 1149.1 JTAG TAP (Test Access Port), and can be chip specific. In the proposed method, a special RTL design is generated in addition to and compatible with typical JTAG TAP logic, and two specific test data registers are designed, as shown in Fig1.

The first test data register is named chain_select_register and has the same number of bits as the number of internal scan chains.  Each bit (ChSel) enables or disables the corresponding internal scan chain.

Fig. 1. Implementation of the 2 specific t...