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A Method and System for Fabricating a Sea of Fins of a Germanium Three dimensional Transistor Structure

IP.com Disclosure Number: IPCOM000237405D
Publication Date: 2014-Jun-17
Document File: 4 page(s) / 98K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for fabricating a sea of fins of a Germanium three dimensional transistor structure.

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A Method and System for Fabricating a Sea of Fins of a Germanium Three dimensional Transistor Structure
Disclosed is a method and system for fabricating a sea of fins of a Germanium (Ge) three dimensional (3D) transistor structure. The 3D transistor structure includes a Ge Field Effect Transistor (pFET) fin and a third to fifth group (III-V) nFET fin.

The method includes a first step of forming the Ge pFET fin (3D) on Shallow Trench Isolation (STI) as shown in fig.1. Here, strained Ge fins are formed from Germanium On Insulator (GOI) substrate and the STI is fabricated by recessing Silicon Dioxide (SiO


2).

Figure 1

As shown in fig.1, the substrate is the GOI substrate.

Fig. 2 illustrates the second step of the fabrication wherein the STI is performed along

with oxide filling or Chemical Mechanical Planarization (CMP).

Figure 2

Fig. 3 illustrates the third step of the fabrication wherein a Nitride or a Photoresist (PR) is deposited on the pFET.

1


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Figure 3

In the fourth step, III-V Indium Gallium Arsenide (InGaAs) nFET 3D fins are formed by selective epitaxial growth from a Ge seed. Here, a Silicon Germanium (SiGe) layer is partially removed by wet etching or Reactive ion Etching (RIE) to form concave shape in the SiGe or Ge seed layer as shown in fig.4.

Figure 4

Here, the Ge seed is formed by chemical etching to obtain a concave Ge seed . Epitaxial (epi) and lattice match III-V material such as, but not limited to, InGaAs are then grown from the conca...