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A Method to Enable Multiple Substrate Thicknesses within a Single Parasitic Technology File

IP.com Disclosure Number: IPCOM000237496D
Publication Date: 2014-Jun-19
Document File: 3 page(s) / 183K

Publishing Venue

The IP.com Prior Art Database

Abstract

Conventionally, VLSI (Very Large Scale Integration) technologies have single substrate/wafer thickness. However, with the advent of 3D technologies and TSV (Through Silicon VIA) enablement, same technology can now have multiple substrate/wafer thicknesses. This calls for parallel enhancement in the parasitic technology file development and analysis to support these new requirements.

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Page 01 of 3

A Method to Enable Multiple Substrate Thicknesses within a Single Parasitic Technology File

Existing PEX Methodology

Existing PEX Methodology for Multiple Substrate Thicknesses
Multiple Substrate Thicknesses require the PEX process to be repeated "n" times

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Page 02 of 3

Proposed PEX Methodology

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Page 03 of 3

Advantages

For Developer:


- Reduced development cycle time


- Simpler methodology


- Reduced susceptibility to quality issues


- For Customer:


- Full compatibility with existing vendor tools & flow


- No additional cost in adapting this method


- Ease of maintenance


- Ease of usage with low susceptibility to user error

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