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Low-temperature ultrathin body MOSFET for 3D integration

IP.com Disclosure Number: IPCOM000237519D
Publication Date: 2014-Jun-19
Document File: 3 page(s) / 36K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a device structure and process flow that is compatible to the maximum processing temperature allowed in Back End of Line (BEOL). Hence, it enables cost-effective 3D integration of a stack of thin film transistors with high quality.

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Low-temperature ultrathin body MOSFET for 3D integration

Three-dimensional (3D) integration is an emerging technology to increase the use of the wafer real estate in order to increase chip functionality and reduce cost. Several methods have been proposed for 3D integration. In the conventional approach, two or more wafers are processed separately to fabricate different device layers and then bonded to achieve 3D integration. The main drawback of this approach is that even though the final chip has a smaller area, the cost of processing the wafers makes the final product expensive. In addition, good alignment between the wafers is required; otherwise, large wafer real estate is needed for the bonding pads.

In another approach, some of the devices are fabricated on thin films of semiconductor (usually poly-Silicon (Si) or poly-Silicon Germanium (SiGe)) that are deposited on an insulating layer such as Silicon Oxygen (SiO2) or Silicon Nitride (SiN). This approach is more cost effective, but the fact that the maximum Back End of Line (BEOL) processing temperature is around 500°C seriously limits the material and processing options.

The novel contribution is a device structure and process flow that is compatible to the maximum processing temperature allowed in BEOL. Hence, it enables cost-effective 3D integration of a stack of thin film transistors with high quality. The technique uses metal-induced lateral crystallization to form near single crystal semiconductor in the channel area and uses the concept of dopant segregation Schottky Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) to enable low-temperature device fabrication.

Starting with a wafer with FEOL devices already fabricated and covered by at least one layer of BEOL dielectric, a layer of a-Si or a-SiGe with a thickness less than approximately 20 nm is deposited using a method such as Physical Vapor Deposition (PVD) or low-temperature Chemical Vapor Deposition (CVD) (T<500oC). This layer is then patterned to active regions using mesa isolation. A hig...