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Structure and Method for Vertical ESD devices in Bulk and SOI

IP.com Disclosure Number: IPCOM000237520D
Publication Date: 2014-Jun-19
Document File: 3 page(s) / 40K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed are a structure and method for electrostatics discharging (ESD) devices in both bulk and Silicon on Insulator (SOI) with deep trench technology.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 62% of the total text.

Page 01 of 3

Structure and Method for Vertical ESD devices in Bulk and SOI

Conventional lateral Negative-Positive-Negative (NPN) for electrostatics discharging (ESD) requires silicide-blocking on source/drain (S/D) regions for current ballasting, resulting in increased device size. In addition, conventional lateral NPN using thin and medium oxide Negative Field Effect Transistors (NFETs) are susceptible to lower failure current due to gate oxide breakdown during ESD. Lateral NFET based NPNs in Silicon on Insulator (SOI) suffer from lower failure currents due to thin SOI.

This disclosure provides a structure and method for ESD devices in both bulk and SOI with deep trench technology.

The first embodiment is shown in Figure 1. The P+, N+, and N-band form a vertical ESD NPN structure. The P+ functions as the base (B), the N+ functions as the emitter
(E), and the N-band functions as the collector (C). The structure is compatible with embedded Dynamic Random Access Memory (eDRAM) flow. The P+ ring can be a single ring around an array of vertical NPNs.

Figure 1: Embodiment #1

The second embodiment is shown in Figure 2. The P+, N+, and N-band form a buried lateral NPN ESD structure. The N+ buried plates of two adjacent deep trenches serve as the collector (C) and the emitter (E), and the P+ serves as the base (B). Nanowires (NWs) and N-band are electrically connected to the buried plates. Contacts are formed at the wafer surface by silicide and metallization.

Figure 2: Embodiment #2...