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Output Slew Rate Control for a Low-Voltage Differential Driver

IP.com Disclosure Number: IPCOM000237523D
Publication Date: 2014-Jun-19
Document File: 7 page(s) / 87K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is output slew rate control for a low-voltage differential driver.

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This is the abbreviated version, containing approximately 34% of the total text.

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Output Slew Rate Control for a Low -

The output load on a CMOS I/O circuit is one of the factors that limit the speed of operation that can be realized. There are two generally accepted techniques utilized when the loading is too high which fall under the term of "precompensation." In both techniques, there is an additional output driving stage that is used to provide an increase in driving current to reduce the transition time of the output to allow for higher frequency of operation. It should also be mentioned that these types of I/O circuits need to have appropriate termination resistance to suppress transmission line reflections.

    The first technique has input data-dependent circuitry that enables a parallel programmable higher current drive on the incident transition for a bit time and then disables this in the next bit time, providing there is no need for the output to change state. This could, and usually does, require a training period to arrive at the proper setting for the additional current drive needed. The programmability and bit time duration is more complex than the development cycle allows for the design activity of focus.

    The second technique utilizes a high-pass filter on the parallel driver to provide current to switch the output and get reduced transition times. While this is attractive in theory, the capacitance needed to drive the load at the speed of interest becomes too large in value and physical size if integrated into the I/O cell. The solution requires a minimum slew for a particular load, and not have a training period and neither of the two known techniques would have provided this.

    The core idea of this disclosure can be broken down into two features. First, a typical differential driver will have a tail current device for both the header and footer of the output stage. Also, this driver will have an opamp that would be used to set the output common mode voltage to a reference. The concept of a parallel driver (boost driver) is not new, but to have one that has current tracking between with the main drive stage is. This boost driver is not selected
to be active by data dependency (typical precompensation) but by input transition direction (rising or falling) and, when active, the current provided is a ratio of the main drive current. Second is by having this current tracking of the boost to main drive stages, there needs to be current mirrors introduced to isolate the main drive tail device bias voltages from the boost drive. This is needed because the switching of the boost drive can corrupt the opamp operation. These two features together allows a faster output slew rate of the driver without the need for control inputs or training periods.

    This IO circuit is a two-part low voltage differential signal (LVDS) driver. The circuit consists of two output stages tied to the outputs in parallel. Each output stage would require an accompanying pre-drive circuit (see Figure 1 below). The first main driver i...