Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

A Method for Fabricating a Replacement Gate MOSFET with an Asymmetric Spacer

IP.com Disclosure Number: IPCOM000237524D
Publication Date: 2014-Jun-19
Document File: 4 page(s) / 119K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is disclosed for fabricating a replacement gate Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with an asymmetric spacer to reduce parasitic capacitance and lower extension resistance.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 4

A Method for Fabricating a Replacement Gate MOSFET with an Asymmetric Spacer

Disclosed is a method for fabricating a replacement gate Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with an asymmetric spacer to reduce parasitic capacitance and lower extension resistance.

The replacement gate MOSFET with the asymmetric spacer is applicable for a plurality of devices such as, but not limited to, a Partially Depleted Silicon on Insulator (PDSOI), an Extremely Thin Silicon on Insulator (ETSOI) and a fin Field Effect Transistor (finFET).

In an exemplary embodiment, the replacement gate MOSFET with the asymmetric spacer is applied to the ETSOI.

Fig. 1 illustrates the first step of placing a dummy gate over an ETSOI layer .

Figure 1

As illustrated in fig. 1, the substrate consists of an insulator layer which may include , but is not limited to, the Buried Oxide (BOX) layer and the ETSOI layer. Here, the layer on top of the BOX layer represents the ETSOI layer. As shown in fig.1, the pointer 1 to the middle portion of the substrate indicates the dummy gate dielectric . Here, the dummy gate includes, but is not limited to, an oxide, a polysilicon, an amorphous silicon, a nitride, or a combination of the materials that are placed over the ETSOI layer . The pointer 2 on the right side of the substrate indicates a spacer made of silicon nitride that is placed over the ETSOI layer. The blue region represents the Raised Source and Drain (RSD) parts over the ETSOI layer that are raised on both sides of the dummy gate to form a MOSFET channel.

Fig. 2 illustrates the second step of depositing a thin spacer material over the ETSOI

1


Page 02 of 4

layer.

Figure 2

As shown in fig. 2, a dielectric such as an oxide is deposited over t...