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%AMC% Apparatus to Provide Multiple Virtual Supply Voltage Points Through Selective Activation of Header Devices

IP.com Disclosure Number: IPCOM000237597D
Publication Date: 2014-Jun-26
Document File: 1 page(s) / 48K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to provide incremental augmentation of the current per-core power gating so that multiple voltage tap points are available to the processor core. The principal idea of this invention is to allow a degree of programmability in enabling (on request) only a small subset of the transistor switches to be turned ON, in such a manner as to provide at least one additional, intermediate voltage point (between full Vdd and ~0 or ground) to the processor core.

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Apparatus to Provide Multiple Virtual Supply Voltage Points Through

      Apparatus to Provide Multiple Virtual Supply Voltage Points Through Selective Activation of Header Devices

Without investing in on-chip voltage regulation modules (VRMs), which is costly, it is not possible to dynamically change the voltages of individual cores within a multi -core processor chip. Without such capability (i.e., per-core or per-lane in the case of attached accelerator chips), dynamic voltage/frequency scaling (DVFS), dynamic power management algorithms at the chip level are fundamentally constrained . Per-core power-gating technologies have recently been implemented in real design . However, such designs provide only an on-off switch capability; intermediate supply voltage points are not available. Hence, fine-grain per-core DVFS algorithms cannot be implemented in such a setting.

There are currently no known solutions to this problem, other than investing into on-chip

VRMS, which is unattractive from a cost-benefit viewpoint. A solution is needed that provides incremental augmentation of the current per -core power gating so that multiple voltage tap points are available to the processor core.

Current approaches selectively turn on or off header devices to achieve different voltages at circuit. Core- or accelerator-level power gating (prior art) is generally implemented by using an array (or column) of header (or footer) transistors (switches) that:


• In their ON state connect the...