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Method of SiP Packaging for Semiconductors

IP.com Disclosure Number: IPCOM000237620D
Publication Date: 2014-Jun-27
Document File: 3 page(s) / 506K

Publishing Venue

The IP.com Prior Art Database

Abstract

A package design is presented that better uses the space inside the packaging for TBGA, which can also allow for increased functionality and more I/Os yet at a lower cost. The package also has good thermal conductivity.

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TITLE

Method of SiP Packaging for Semiconductors

ABSTRACT

A package design is presented that better uses the space inside the packaging for TBGA, which can also allow for increased functionality and more I/Os yet at a lower cost.  The package also has good thermal conductivity.

CONTENT

Packaging Process Flow:

1.         Substrate mounting:

Ø          Laminated substrate with all the pre-designed circuitry is aligned on a mounting tape for the ease of subsequent handling and die bond process flow.

2.         Die bond Process:

Ø          Single or multiple IC chips are die-bonded on designated locations, which could be single die or stacked dies.

3.         Interconnection process between the IC chip to the substrate:

Ø          Either wire bond, ball bump, Cu pillar, or flip chip is carried out to electrically connect the IC chips to the substrate.

4.         1st encapsulation Process:

Ø          A first molding process is performed to encapsulate all of the IC chips.

5.         Heat Spreader Attach

Ø          The surface of the molded part is flipped over, and then a metal heat spreader is attached to the molded part using tape or another form of high temp adhesive layer.

6.         The other side (non-heat spreader side) of the substrate is exposed and an additional IC chip can be die-bonded, and electrically connected to this other side of the substrate,

7.         2nd encapsulation process:

Ø          A second molding process is performed to encapsulate the additional IC chip and any bond wires or interconnects.

Important Components: