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Method to tune wafer bow to enable packaging

IP.com Disclosure Number: IPCOM000237685D
Publication Date: 2014-Jul-02
Document File: 1 page(s) / 42K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a set of methods to vary the dielectric stress of thicker Back End of Line (BEOL) levels. This approach allows the end of the fab wafer bow, specifically the backside grind, to be altered to induce a flatter wafer during and after packaging.

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Method to tune wafer bow to enable packaging

Continually back thinning chips to increasingly thinner conditions enables the components of advanced devices, such as smart phones, to withstand the inherent stresses within the wafer during fabrication. However, this can lead to problems during packaging manufacturing. For example, current wafer backside thinning is starting to go below 280um and even thinner. Further, for chips with very thick interconnect wires contained therein, these stresses become significant and thus must be managed.

The solution is to vary the dielectric stress of thicker Back End of Line (BEOL) levels. This approach allows the end of the fab wafer bow, specifically the backside grind,
to be altered to induce a flatter wafer during and after packaging.

The method adjusts BEOL 3um thick films to increase the associated compressive stress from 40 MPa to 80 or even 120 MPa. Further, multiple levels can be adjusted in a similar manner to gain even greater wafer stress adjustment.

The solution comprises three core methods. The first is a method to alter global

wafer conformality after backside grind by varying wafer level film stress. This is done by varying: one 3.0um thick BEOL damascene wire's dielectric stress from 40 to 120 MPa compressive, and two 3.0um thick BEOL damascene wires' dielectric stress from 40 to 120 MPa compressive. The second method is to alter global wafer conformality after backside grind by varying wafer level film stress f...