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FEOL oxide under waveguide for photonics chip

IP.com Disclosure Number: IPCOM000237686D
Publication Date: 2014-Jul-02
Document File: 3 page(s) / 223K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a Front End of Line (FEOL) oxide under waveguide process that ensures good coupling between an optical fiber and a waveguide.

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FEOL oxide under waveguide for photonics chip

Silicon photonics chips are in development for high-speed interconnects between die. Waveguides can be easily built on Semiconductor on Insulator (SOI) wafers

and integrated with Complementary Metal-Oxide Semiconductor (CMOS) devices.
[1] However, a connection must be made between an "off-chip" optical fiber and the

waveguide. Out-of-plane coupling uses an optical grating to couple light from the fiber to the waveguide, but this limits the optical signal to one wavelength. In-plane coupling allows broadband transmission (multiple wavelengths, and therefore higher bandwidth). [2] However, achieving high coupling efficiency is difficult.

The basic reason for loss for in-plane coupling is that the core of the optical fiber has a much larger diameter than the Silicon (Si) waveguide. The loss can be reduced using an inverse taper on the Si waveguide for improved coupling. For maximum coupling, it is important to surround the Si waveguide with Silicon Dioxide (SiO2). If the Si substrate is not removed under the waveguide, then some light couples into the substrate and the signal is reduced.

Figure 1: Problem: optical fiber must couple to Si waveguide

The novel contribution is a method to etch the Si substrate from the front side before patterning the active area. Then, the trench is filled with SiO2, so that the bottom of the waveguide is covered with SiO2 (2 to 10 um). The Si waveguide is essentially surrounded by SiO2, en...