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A Method for Simulating Resistance of Local Interconnects in Semiconductor Devices

IP.com Disclosure Number: IPCOM000237725D
Publication Date: 2014-Jul-07
Document File: 4 page(s) / 131K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is disclosed for simulating resistance of local interconnects in semiconductor devices to predict an appropriate fin Field Effect Transistor (finFET) drain current.

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Page 01 of 4

A Method for Simulating Resistance of Local Interconnects in Semiconductor Devices

Disclosed is a method for simulating resistance of local interconnects in a fin Field

Effect Transistor (finFET) device in order to predict the drain current of the finFET.

Figure 1 illustrates a cross section view of a local interconnect (CA) located at the source (or drain) side of a finFET device. The finFET includes multiple fins (Nfin fins).

The bottom of the local interconnect (CA) is connected to the multiple fins. The top of the local interconnect is contacted by a contact (V0), and the position of contact (V0) is outside a diffusion (RX) region.

Figure 1

In Figure 1 the blue color arrows indicate a drain current (J) of the plurality of fins that enters into the local interconnects (CA) from its bottom. In an exemplary embodiment, the drain current is simulated, when a contact (V0) is outside the RX region. As shown in Figure 1, a portion of the local interconnect that is within the diffusion (RX) region is represented in yellow color and and another portion of the local interconnect that is outside the diffusion (RX) region is represented cyan color. The drain current is perpendicular to the far right edge of the cyan color region.

Figure 2 illustrates the method step of adding capacitors to a grid of resistors placed in a simulation domain when the contact is outside the diffusion (RX) region.

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Figure 2

The yellow color region in Figure 2 corresponds to the yellow color region in Figure 1, and the cyan color region corresponds to the yellow color region in Figure 1. A set of capacitors that have equal capacitance density is added at the bottom of the local interconnect (CA) to ensure an injection of equal amounts of the drain current density at the bottom of the local interconnect (CA) from the plurality of fins. The outside node of each capacitor at the bottom of the local interconnect (CA) has an equal potential. The outside node of each resistor located at the right most e...