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EG integration with tight fin pitch

IP.com Disclosure Number: IPCOM000237739D
Publication Date: 2014-Jul-08
Document File: 2 page(s) / 58K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed are a method and structure form forming integrating thick gate dielectric (EG) Field Effect Transistors (FETs) with tight fin pitch. With this method, EG and thin gate dielectric (SG) FETs have the same fin pitch, easing challenges with fin patterning.

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EG integration with tight fin pitch

A fin Field Effect Transistor (FET) becomes a real technology at 22nm and beyond. In addition to thin gate dielectric (SG) FETs, a thick gate dielectric (EG) FET is needed to support high voltage applications. For 10nm, an EG dielectric is formed by depositing ~5nm EG oxide and then followed by ~2nm high-k, work function metal (WFM), and a low resistance tungsten (W) gate fill. For 7nm, fin pitch is projected to be ~30nm. With a fin width of 8nm, there is not enough room left for EG oxide, high-K (HK), WFM, or W fill. For example:

• 30nm fin pitch, 8nm Dfin => 22nm gap
• Per fin sidewall, EG oxide: 5nm, HK: 2nm, WFM: 5nm => 12nm per side => 24nm total > 22nm fin gap (this does not take account of fin pitch walking yet)

Using a relaxed fin pitch for EG and tight fin pitch for SG is one solution . However, such a multiple fin pitch approach has a few disadvantages such as challenges in patterning, epitaxy, loading, as well as loss of device area due to relaxed fin pitch.

A method is needed to provide EG integration for 7nm with tight fin pitch.

The novel contribution is a method and structure form forming integrating EG FETs with tight fin pitch. With this method, EG and SG FETs have the same fin pitch, easing the fin patterning challenge. Furthermore, EG FET and SG FETs share the same HK and WFM, but the EG FET has a thinner fin, resulting in desired higher Vt of EG FET.

The process flow for implementing the method follows :...