Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Zero latency dynamic data stream scheduling in a resource-shared DSP hardware accelerator

IP.com Disclosure Number: IPCOM000237760D
Publication Date: 2014-Jul-09
Document File: 4 page(s) / 231K

Publishing Venue

The IP.com Prior Art Database

Abstract

A DSP hardware accelerator that processes intensive algorithms, involving many multiplies and additions (million of operations per second) consumes a high number of MIPS or processor cycles if implemented in software. By offloading some of the functions to hardware we can free MIPS for other software programs. Compared to a generic DSP processor, the function specific HW accelerator has the advantage of making processing faster, but if not optimized for area and power, it can have too much overhead in the SoC. For a pipelined HW accelerator, it loses its advantage of area and power if multiple instances of the accelerator are used for multiple output data streams. Thus, there is a need for HW sharing between various output streams, which may be accomplished by increasing the clock frequency with SW scheduling the HW accelerator between different data streams.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Zero latency dynamic data stream scheduling in a

resource-shared DSP hardware accelerator

Abstract

A DSP hardware accelerator that processes intensive algorithms, involving many multiplies and additions (million of operations per second) consumes a high number of MIPS or processor cycles if implemented in software.  By offloading some of the functions to hardware we can free MIPS for other software programs.

Compared to a generic DSP processor, the function specific HW accelerator has the advantage of making processing faster, but if not optimized for area and power, it can have too much overhead in the SoC.  For a pipelined HW accelerator, it loses its advantage of area and power if multiple instances of the accelerator are used for multiple output data streams.  Thus, there is a need for HW sharing between various output streams, which may be accomplished by increasing the clock frequency with SW scheduling the HW accelerator between different data streams.

Introduction

A resource shared pipelined DSP HW accelerator that has the following requirements:

•       Constant throughput at the output for all output streams

•       Identical processing for all data streams

•       Compute intensive pipeline stages, for example interpolation filters

And has the following challenges:

•       Switching latency while switching among data streams

•       Scalability, increasing number of streams at design level

•       Efficient utilization of egress buffer while supporting multiple output and input sampling rates

SW based scheduling has the following problems:

•       High switching latency

•       Decreased throughput as data stream count increases (at constant clock)

•       Large egress buffer to accommodate indeterministic switching latency

Thus, there is a need for a HW based dynamic switching scheme for a resource shared, pipelined HW accelerator for:

•       Saving MIPS for SW

•       Efficient usage and optimum size of egress buffer

•       Deterministic switching latency with zero downtime during switching

Design and Implementation of Proposed Solution

We propose a scheme to dynamically switch the DSP...