Browse Prior Art Database

Structure and Method to Form a Buried 2T NVM Cell (Control Gate First or Select Gate First) That Can Be Integrated with Hi-k Dielectric / Metal Gate Logic

IP.com Disclosure Number: IPCOM000237797D
Publication Date: 2014-Jul-11
Document File: 3 page(s) / 144K

Publishing Venue

The IP.com Prior Art Database

Abstract

In metal gate last and high-k first / metal gate last logic processes, a CMP step is needed to planarize the final gate structure. This CMP step makes it difficult to integrate planar NVM prior to logic gate formation because the NVM bitcell height is limited to the height of the logic gates. This document provides a structure and method to decouple NVM bitcell formation from the logic gate CMP step thereby eliminating the NVM bitcell height restriction. With no height restriction, the optimal nanocrystal stack and gate conductor thicknesses can be chosen. The approach described in this document could be utilized in planar and non-planar (i.e., FinFET) logic integrations.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Structure and Method to Form a Buried 2T NVM Cell (Control Gate First or Select Gate First) That Can Be Integrated with Hi-k Dielectric / Metal Gate Logic

Abstract

In metal gate last and high-k first / metal gate last logic processes, a CMP step is needed to planarize the final gate structure. This CMP step makes it difficult to integrate planar NVM prior to logic gate formation because the NVM bitcell height is limited to the height of the logic gates. This document provides a structure and method to decouple NVM bitcell formation from the logic gate CMP step thereby eliminating the NVM bitcell height restriction. With no height restriction, the optimal nanocrystal stack and gate conductor thicknesses can be chosen. The approach described in this document could be utilized in planar and non-planar (i.e., FinFET) logic integrations.

Description

Two embodiments are described in this document:  Control Gate (CG) First and Select Gate (SG) First.

Embodiment 1 - Control Gate First

A) Perform Control Gate Well Photo and Implant Followed by S/D Photo and Implant (S/D’s are

formed by a chained implant that extends to bottom of nanocrystal stack).

B) Form NVM Bitcell Cavity

C) Deposit Nanocrystal Stack

D) Deposit Control Gate (Could be Poly or Metal)

E) Perform CMP

F) Form Select Gate Trench (depth needs to be roughly even with bottom of nanocrystal stack)

G) Form Oxide Spacer

H) Perform Select Gate Well Photo and Implant (Effectively self-aligned due to S/D on left

               and control gate on right)

I) Deposit Select Gate Oxide (Could be thermal...