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A Method and System for Performing Fabric Bus Tagging for Improved Fabric Interface Recoverability

IP.com Disclosure Number: IPCOM000237825D
Publication Date: 2014-Jul-15
Document File: 3 page(s) / 80K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for performing fabric bus tagging for improved fabric interface recoverability.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 51% of the total text.

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A Method and System for Performing Fabric Bus Tagging for Improved Fabric Interface Recoverability
Disclosed is a method and system for performing fabric bus tagging for improved fabric interface recoverability.

The method and system utilizes bits on a main interface and avoids a sideband bus. The example explains a shared control/data bus that can be utilized for dedicated interfaces to control only or data only interfaces.

Example: Control


Bit0 Even Odd
Beat0 1 1 [Control vs. Data indicator]

Beat1 0 1 [Odd indicator]

Beat2 CV CV [Control/Interrupt=1 (vs. Idle=0) Indicator] Beat3 DCV - [Delayed Control/Interrupt Indicator]

Data
Bit0 Even Odd
Beat0 0 0 [Control vs. Data indicator]

Beat1 0 1 [Odd indicator]

Beat2 - -
Beat3 DCV -

As shown in the example, a logical frame on a fabric bus consists of multiple beats of control/data and Error Correcting Code (ECC) bits. Information related to the multiple beats of control/data and ECC bits is transmitted on an interface in frame pairs such as even or odd pair.

The ECC code provides a Single-bit Error Correction (SEC) and Double-bit Error Detection (DED) along with reserved syndromes to transmit some Special UE information.

As shown in the example, Bit 0 of beat 0 of a bus frame indicates a frame type. When the bit value is 1, the frame either contains control information or is idle. Here, control

1


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or data frames are always transmitted in pairs.

During a condition of bit 0 of beat 1, both control and data frames contain an even/odd bus frame indicator to communicate phase of a sending chip to a receiving chip. During a condition of Bit 0 of beat 2, both even and odd control frames carries a Control Valid (CV) indicator to communicate whether or not a Uncorrectable Error (UE) is in either control frame of this pair. If the UE is in either the control frame then critical information such as, but not limited to, a coherency message is lost. Here, two copies of the CV in a control frame pair, one in each fr...