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Microserver architecture

IP.com Disclosure Number: IPCOM000237851D
Publication Date: 2014-Jul-16
Document File: 3 page(s) / 42K

Publishing Venue

The IP.com Prior Art Database

Abstract

There are two issues with current microserver technology: Limited memory per node (including the lack of ability to average memory usage across several microservers), and the required high connectivity amongst microservers and to the rest of the data-center (e.g. to storage). These problems are solved by means of a controller chip, which has three ports: A port to a plurality of microserver compute chips, a port to memory chips, and a port to the network (system & scaling). Such a configuration allows small SOC CPU packages (without memory pins), redundant and dynamically scaled per-microserver memory sizes, MoN (memory over network) access to memory chips attached to other controller chips in the system for further scaling.

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Microserver architecture

    Microservers are becoming more and more contenders for server applications for certain workloads. Value proposition is in density and power efficiency. There are two issues with current microserver technology: Limited memory per node (including the lack of ability to average memory usage across several microservers), and the required high connectivity amongst microservers and to the rest of the data-center (e.g. to storage). These problems are solved by means of a controller chip, which has three ports: To microserver compute chips, to memory chips, to network.

    In todays microserver systems, 'normal' server CPUs are used. They have limits in the amount of memory which can be connected, sometimes even lack the ability to use ECC memory. In addition, the memory bus (i.e. DDR3) is a high-pin-count and low-power-efficiency interface.

    It is proposed to use a ultra-low-power serial link bus to connect a plurality of microserver SOCs CPU to the controller chip. The advantage is in excellent power efficiency, low pin count (hence lower cost package, higher density) and in the ability to combine memory and network traffic on one interface. A plurality of microserver SOC (consisting of only: a plurality of CPU cores, cache, a unified memory&network controller, and a network interface) are connected to one or several (e.g. 2 for RAS) control chips. The control chips analyze the data traffic, and funnel the data traffic either to memory requests, or to network requests. The control chip can add encryption and/or compression. The control chip has a number of DIMMs attached.

It translates memory request microserver addresses to DIMM adresses. The control chip can adaptively assign memory regions to the various attached microserver SOCs. By doing so, each microserver can have whatever memory its current workload requires. This leads to an averaging of memory needed, which reduces the amount of memory to be installed (lower cost, lower power). In addition, it means that a microserver can have all of the available memory for workloads with large memory requirements. In particular, it is possible to dedicate more memory to a microserver SOC in this proposed configuration that what would be possible in 'traditional' microserver designs, where the amount of memory attached to one microserver chip is limited due to pin/power/space limitation.

    The control chip can have many DIMMs attached, hence it can exploit memory striping (in the sense of memory RAID) to achieve high reliability with ultra cheap commodity DIMMs (be it regular DIMMs or for higher density SO-DIMMs). Hereby, it can implement chip-kill and/or DIMM-kill reliability feat...