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Method for Automatic Centralized Checker Generation in IP-based SoC

IP.com Disclosure Number: IPCOM000237884D
Publication Date: 2014-Jul-17
Document File: 6 page(s) / 453K

Publishing Venue

The IP.com Prior Art Database

Abstract

SoC (System on Chip) is a popular high-performance, low power and low cost chip. In order to meet tight schedules, many digital, analog and mixed-signal IPs (Intellectual Property) are integrated on an SoC. Verification engineers have to spend a lot time studying the IP functions, even some detailed critical signals in the design so that they can develop SoC checkers for verification. This article introduces an automatic centralized checker generation method that can generate checkers based on SoC verification methods and environment automatically and these checkers can be used by different engineers easily.

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Method for Automatic Centralized Checker Generation in IP-based SoC

ABSTRACT

SoC (System on Chip) is a popular high-performance, low power and low cost chip.  In order to meet tight schedules, many digital, analog and mixed-signal IPs (Intellectual Property) are integrated on an SoC.  Verification engineers have to spend a lot time studying the IP functions, even some detailed critical signals in the design so that they can develop SoC checkers for verification.  This article introduces an automatic centralized checker generation method that can generate checkers based on SoC verification methods and environment automatically and these checkers can be used by different engineers easily.

KEYWORDS

Checker Generation, IP, Mixed-signal, Assertion, Coverage

1.     INTRODUCTION

IP based SoC design methods are popular and important for generating SoCs.  Mixed signal SoCs have been main-stream because more features are integrated into a single chip.  In order to implement flexible and configurable chips and meet market requirements, more and more functional operation modes are defined and implemented in current processing devices, such as some low power modes (STOP, LLS, etc,), some clock modes (FAST, SLOW, etc.), and some test modes (CHIP_SCAN, SRPG_SCAN, IDDQ_SCAN, RAMBIST, etc.).

The SoC team and IP designers have met some problems.

(a) Verification engineers have to create many checkers to check if the IPs are in expected state when chip is running in the functional mode but it is very difficult for every verification engineer to know what each signals’ expected value.

(b) It is very different for every IP designer to know all functional modes in each SoC and cannot send out one signal list that is needed to check.

(c) Some checkers are implemented inside IPs (AMS model or RTL code), but these checkers are not easily configured for some functional modes defined in the SoC.  And these checkers may be described with embedded PLI (Programming Language Interface), functional language, which makes it difficult to use in the SoC.

(d) Some analog signals are easy to implement but difficult to check because the analog model depends on the simulator.

(e) It’s not easy to generate one obvious coverage report to indicate whether or not the checkers are complete.

(f) Different SoC verification engineers including DFT engineers have to create almost the same tasks for some functional modes, and run simulation by each engineer, which is inefficient.

2.     WHAT IS THE MOTIVATION?

The authors faced difficulties on an SoC design because some checkers for critical signals in IPs were not correct or missed, which resulted in schedule delay.

(a) In ChipA, one pad PUE (pull up enable) signal is not put in safe state during scan mode, which caused big leakage in real silicon.  After big effort in failure analysis process, the issue was identified.  Silicon re-spin had to be done for this defect.

(b) In ChipB, one analog module was updated during the development p...