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System and Method to Achieve Deterministic Latency from Asynchronous FIFO

IP.com Disclosure Number: IPCOM000237885D
Publication Date: 2014-Jul-17
Document File: 11 page(s) / 1M

Publishing Venue

The IP.com Prior Art Database

Abstract

In current generation SoCs/IPs, there are many asynchronous clock domains such that digital pulses/signals often must be transferred from one clock domain to another clock domain. Special logic is needed to handle the data transfer across asynchronous clock domains. The synchronization methods used in-deterministically synchronize data between two asynchronous clock domains, that is, synchronized data may be recognized in different cycles at different times across Process, Voltage and Temperature (PVT). In this paper, we propose a method of getting a deterministic response from an asynchronous FIFO used between two source-asynchronous domains that are integral multiples of each other. The method uses a Synchronous Clock Phase Selector (SCPS) in which continuous switching data (CSD) generated from a source clock is oversampled by a destination clock. Oversampling logic is followed by a one-hot combinatorial algorithm that determines the unique phase that will act as the sampling clock (for the destination clock domain) to deterministically sample the data from source clock.

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System and Method to Achieve Deterministic Latency from Asynchronous FIFO

Abstract

In current generation SoCs/IPs, there are many asynchronous clock domains such that digital pulses/signals often must be transferred from one clock domain to another clock domain.  Special logic is needed to handle the data transfer across asynchronous clock domains.  The synchronization methods used in-deterministically synchronize data between two asynchronous clock domains, that is, synchronized data may be recognized in different cycles at different times across Process, Voltage and Temperature (PVT).  In this paper, we propose a method of getting a deterministic response from an asynchronous FIFO used between two source-asynchronous domains that are integral multiples of each other.  The method uses a Synchronous Clock Phase Selector (SCPS) in which continuous switching data (CSD) generated from a source clock is oversampled by a destination clock.  Oversampling logic is followed by a one-hot combinatorial algorithm that determines the unique phase that will act as the sampling clock(for the destination clock domain) to deterministically sample the data from source clock.

Background

Conventional synchronization methods try to achieve:

•        Stable data transfer across unrelated driving and sampling clocks,

•        While ensuring removal of meta-stability propagation in the design.

Examples of conventional techniques are two flip-flop synchronizer circuits, asynchronous FIFOs, etc.

In a conventional asynchronous FIFO, Data Write/Read from the FIFO is controlled by Write/Read pointers.

Ø  Write Pointer (generated by Write Clk Domain) is synchronized to Read Clk Domain.

Ø  Read Pointer (generated by Read Clk Domain) is synchronized to Write Clk Domain.

Let us consider various cases of frequency combinations and operation in a conventional asynchronous FIFO.

Case 1: Write clk freq = Read clk freq

Ø  Synchronizer on Write/Read pointers may result in In-Deterministic Response from FIFO.

Ø  Data availability may randomly shiftfor different transactions or different parts or voltage or temperature conditions.

Case 2: Write clk freq < Read clk freq

Case 3: Write clk freq > Read clk freq

Motivation

Our motivation is to remove the in-deterministic nature of data transfer between two asynchronous clock domains, which could be due to different clock source or PVT variation.

Applications impacted and of concern are:

    1.  Due to indeterministic nature of data transfer between tester clock and SoC clock, tester pattern stabilization issues occur on ATE (Automatic Test Equipment), which raises the need for a lot of extra effort for every SoC.
    2.  Timing critical applications (like medical, automotive) where an accurately timed response is required.

Description of Proposed Method

We propose a deterministic synchronization scheme that enables data transfer in determined sampling clock cycles.

Ø  It determines a “unique phase” which will act as the sampling destination cl...