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Method of Saving System Power in Deep Sleep Mode Using Programmable FSM with Fast System Restore

IP.com Disclosure Number: IPCOM000237897D
Publication Date: 2014-Jul-18
Document File: 6 page(s) / 361K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method for fast deep sleep mode entry and system restore is presented that achieves a low deep sleep power of less than 200mW, facilitating compliance with the Energy Star requirement of less than 0.5W at AC. The system deep sleep can have several different personalities that emanate from different use case applications requiring different IPs to be ON or OFF. Each of the personalities can have some finite differences in entering, remaining in deep sleep, and exiting from deep sleep. These can be different across SoCs. Also, the system is restored from deep sleep state in a fast manner, for example less than 1 second.

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Method of Saving System Power in Deep Sleep Mode Using Programmable  FSM with Fast System Restore

Abstract

A method for fast deep sleep mode entry and system restore is presented that achieves a low deep sleep power of less than 200mW, facilitating compliance with the Energy Star requirement of less than 0.5W at AC.  The system deep sleep can have several different personalities that emanate from different use case applications requiring different IPs to be ON or OFF.  Each of the personalities can have some finite differences in entering, remaining in deep sleep, and exiting from deep sleep. These can be different across SoCs.  Also, the system is restored from deep sleep state in a fast manner, for example less than 1 second.

Description

We propose an architectural scheme to achieve a minimal power target along with faster system restore in a wide variety of application use cases.

•          Achieve minimal power target  (1st aspect)

•          All the IPs that are primary wakeup sources or which are responsible for network presence are ON, the rest are powered OFF, this includes PLLs, CPUs, memory controllers, system interconnect, etc.  Even within the powered ON IPs, only sections required during deep sleep are powered ON and clocked, the  other sections are powered OFF.

•          The IPs that are ON are clocked with much slower clock (SoC reference clock), to save dynamic power.  If any IP requires a clock that is faster than the SoC reference clock, clock doublers are used to generate the faster clock instead of PLL that consumes more power.

•          Address a variety of use case applications without hardware changes in the future (2nd aspect)

•          A programmable Finite State Machine (FSM) caters to a wide variety of use case scenarios.  Based on the scenario, the following can be programmed:

•          Powering OFF IP/subsystem in a personality or SoC.

•          Selective Clock gating of a subsystem based on personality

•          Selection of Wake up sources 

•          Configurable preemption of events for deep sleep entry and exit

•          Dependency and timing relation between different events from deep sleep entry to system restore.

•...