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Updating Content in Single Port Memory with Read Busy Control Interface to Optimize Area and Power

IP.com Disclosure Number: IPCOM000237898D
Publication Date: 2014-Jul-18
Document File: 3 page(s) / 304K

Publishing Venue

The IP.com Prior Art Database

Abstract

In some SoCs, feature configuration registers are mapped to a single port memory. In some applications, the particular configuration memory contents must be updated dynamically while the interface is always read busy. The natural solution to this problem is to add a shadow memory and then switch between memories whenever there are configuration changes. Another solution is to have a dual port memory. Both of these solutions are costly in terms of area and power as well the software to maintain the configuration history and keep updating in the shadow configuration memory every modification cycle. We propose using dedicated logic that helps software update the configuration memory without impacting the read busy traffic.

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Updating Content in Single Port Memory with Read Busy Control Interface to Optimize Area and Power

Abstract

In some SoCs, feature configuration registers are mapped to a single port memory. In some applications, the particular configuration memory contents must be updated dynamically while the interface is always read busy. The natural solution to this problem is to add a shadow memory and then switch between memories whenever there are configuration changes. Another solution is to have a dual port memory. Both of these solutions are costly in terms of area and power as well the software to maintain the configuration history and keep updating in the shadow configuration memory every modification cycle. We propose using dedicated logic that helps software update the configuration memory without impacting the read busy traffic.

Introduction

Using single port memory limits the dynamic re-configuration of selective configuration entries since every cycle read happens from this memory. It leads to the following problems.

•       Without stopping/disabling the accelerator traffic reconfiguration is not possible. Hence becomes a road block in a critical feature.

•       Adding one more as shadow single port memory for reconfiguration leads to following issues.

o     Double the impact of area and power

o    Additional overhead on SW to program whole of the configuration memory even though the change is incremental.

The motivation for the proposed method is to provide a cost effective implementat...