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Multicore start execution synchronization

IP.com Disclosure Number: IPCOM000237916D
Publication Date: 2014-Jul-21
Document File: 7 page(s) / 157K

Publishing Venue

The IP.com Prior Art Database

Abstract

In multicore embedded systems it is often desired to have a way to implement a barrier concept for execution synchronization at platform level. This will assure that cores will start execution (approx) in the same time. The challenge is to minimize the skew time between start execution of the cores.

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Multicore start execution synchronization

Abstract:

In multicore embedded systems it is often desired to have a way to implement a barrier concept for execution synchronization at platform level. This will assure that cores will start execution (approx) in the same time. The challenge is to minimize the skew time between start execution of the cores.

Abbreviations and terms:

Trace IP – hw blocks specially designed to monitor program execution or system events and generates a hw trace

Description:

To leverage potential unused Trace IP in deployed embedded products, it was designed a system that use hw blocks for multicore synchronization.

The system comprising in a mechanism of usage of hardware trace in a multicore system/environment to stall cores till desired trigger event. The trigger event can happen when all desired number of cores reach the stall state. A master core is then releasing the mechanism and all cores exit stall state (approx) in the same time. The skew time is influenced by the capability of hw circuit. However, this hw circuit is special designed for hw trace and do not interfere with other chip circuits.

The mechanism that control the system is embedded into a software library that controls trace configuration.

System components are presented in Fig.1.

Fig.1

The mechanism is based on hw trace ability to stall core execution when trace is full. This mechanism is common in today system, because it allows to not lose trace at sudden execution peak. Also the mechanism relies on a common trace sink at platform level, which it is most commonly used approach for hw trace infrastructure in modern embedded systems.

The idea is to configure trace on each core, with stalling attribute enabled and set a common trace sink at a very small size. This way, the cores will enter in stall mode when common sink will fill (extremely fast) and put back-pressure to cores’ FIFOs.

The master core is responsible for checking the barrier condition (e.g., all cores reached the barrier) and also to release the mechanism (e.g., disable common trace sink). This will remove the back-pressure and it will automatically start the cores.

Master core do not stall itself. It will perform common trace sink control/monitor. It will fast return to original code flow after releasing barrier.

Fig.2

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Mechanism is shown in Fig.2 to Fig.7. A possible pseudo-code for barrier code usage is:

Core#0:                  Core#1:      …..   Core#5(master)                          Comments

code                           code                           code      ...