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Method and System for Passing Messages in a PCIe Environment

IP.com Disclosure Number: IPCOM000237920D
Publication Date: 2014-Jul-21
Document File: 5 page(s) / 299K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for passing messages in a Peripheral Component Interconnect Express (PCIe) environment.

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This is the abbreviated version, containing approximately 51% of the total text.

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Method and System for Passing Messages in a PCIe Environment

Disclosed is a method and system for passing messages in a Peripheral Component Interconnect Express (PCIe) environment. The method and system enables same links to be used in a dual mode by using a PCIe as Input/output (I/O) expansion network and as a Sysplex* link. In an I/O mode the PCIe link is a traditional I/O expansion network connecting I/O adapters such as Ethernet or Fiber channel. In a Sysplex mode, the PCIe links interconnect servers. This dual mode allows configuration flexibility without additional Application Specific Integrated Circuit (ASICs) or dedicating physical links to one mode or the other.

A message passing mechanism utilizes a point to point connection wherein a system

z** is available on both ends. The message passing mechanism includes a 32 bit PCIe addresses and is extendable to a PCIe switched topology that includes 64 bit PCIe addresses. The method and system implements PCIe transaction layer buffers to prevent overruns due to memory and resource contention and the only buffers are posted memory write request packet headers and payloads.

For initialization and recovery, the method and system utilizes PCIe link initialization

without configuration space accesses. Further, the method and system utilizes a specialized message queue to exchange initialization and recovery information. These messages have 8 byte payloads. Firmware manages this message queue and ensures its reliability.

Fig. 1 illustrates a topology for message passing using the point to point contact.

Figure 1

Fig. 2 illustrates a topology for message passing using a switched contact

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Figure 2

The method and system utilizes a protocol, wherein all PCI packets are posted memory write requests. PCIe defined memory read requests and completions and configuration space packets are not used. Using only posted memory write requests enables all the PCIe transaction layer buffers to be allocated to this single packet type. Therefore, with

a given transaction buffer space, in the Sysplex mode the cable distance supported by the protocol is maximized. All of the posted memory write request packets have either

an 8 byte or a 256 byte payload. In addition, the method and system utilizes a protocol that repurposes the PCIe address field with Integrated Cluster Bus (ICB-P) information and includes an opcode describing type of packet, message buffer number and routing information for a switched environment. The remaining fields of the PCIe header remain unchanged from the PCIe defined purposes, and this ensures compatibility with PCIe physical, data link, and transaction layer hardware macros.

Fig. 3 illustrates hardware placement in a Processor Unit (PU) chip along with a System Controller Chip.

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Figure 3

Fig. 4 illustrates a session logical layer in a PCIe Environment.

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Figure 4

As shown in fig.4, the to...