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Method and system for efficient page table allocation

IP.com Disclosure Number: IPCOM000238062D
Publication Date: 2014-Jul-30
Document File: 4 page(s) / 42K

Publishing Venue

The IP.com Prior Art Database

Abstract

In post-silicon functional validation, memory access component generates accesses through out all available virtual memory space. In modern systems virtual memory space is extremely large (at least 48 bits in the current designs). Straightforward allocation of radix translation tables for all available virtual space results in huge amount of space for translation tables themselves. The problem is especially challenging when amount of physical memory is limited while virtual space remains huge, for example when running cache-contained.

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Method and system for efficient page table allocation

The post-silicon validation process comprises four interleaved elements: stimulating the design under test (DUT), detecting erroneous behavior, localizing the root cause of the problem, and providing a fix.

    The first two aspects of the post-silicon validation process -- stimuli generation and error detection -- are addressed through the use of bare-metal hardware exercisers, sometimes called software-based self-testing . Exercisers are programs that run on the DUT, generating test-cases, running them, and checking their results.
(See J. Storm. Random test generators for microprocessor design validation;

A. Adir et al. Threadmill: a post-silicon exerciser for multi-threaded processors)

    To ensure high silicon utilization, the exerciser's software must be kept lightweight and simple. This requirement contradicts the demand for high-quality validation, as the latter calls for complex test generation, which in turn implies extensive, complex computation. Solution adopted by exercisers is to shift the preparation of complex data from the runtime to the offline phase that takes place before the software test is compiled and loaded onto the silicon platform. This data is then variably used by the test-case to ensure high testing quality while retaining silicon utilization.
(See Wisam Kadry, Anatoly Koyfman, Dmitry Krestyashyn, Shimon Landa, Amir Nahir, and Vitali Sokhin, "Improving Post-Silicon Validation Effciency by Using Pre-Generated Data")

    Memory Manager is an offline program that allocates intervals required by an exerciser for generation of memory accesses. Memory manager receives the following inputs:


available memory space,


interval allocation requests that describe memory to be used by an exerciser at run-time


hard and soft constraints on the intervals allocation;

Memory manager provides the valid and interesting allocation of the requested intervals within the available memory.

    A DUT may utilize an address translation mechanism, for example, in order to map references to virtual address space into physical memory resources. A hardware-based address translation mechanism may include, for example, translation tables and control registers. Building legal address translation path is a part of test generation requirements. Some address translation algorithms requires using a lot of translation tables located in physical memory to perform translation process.


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    A DUT may support processor virtualization. Processor virtualization is a technique to divide physical processor resources among a set of virtual machines. It hides the physical characteristics of a computing platform from users, instead showing another abstract computing platform. The software that controls virtualization called hypervisor (or host), Hypervisor creates a simulated computer environment for its guest software.

    When virtualization is used, some address translation schemes have multi-stage translat...