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Optimal anti-pads for high-speed backplanes

IP.com Disclosure Number: IPCOM000238074D
Publication Date: 2014-Jul-31
Document File: 4 page(s) / 93K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described are optimal anti-pads for high-speed backplanes.

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This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 4

Optimal anti -

This disclosure relates to the methodologies used to design printed circuit boards in server systems where there are multiple types of signal and power traces required within the printed circuit board. There are high-speed differential signals with speed > 5Gbps and can be as high as 25 to 40 Gbps. There are control signals which would typically be single ended in the 400 kHz range and then power to distribution in the DC range.

    This disclosure presents an optimal multi-parameter anti-pad solution. On top, a shared anti-pad for the differential pair to improve signal integrity, the middle to optimize power distribution, and the bottom to enable back-drilling while maintaining maximum wireability. With the webs between the vias on the lower layers, this maintains the ground reference plane for orthogonal wiring. With rectangular or oval anti-pads wiring with no ground webs between the signal circuit wiring has to run east/west or north/south not on the diagonal as enabled in this design.

    Holistically, it is preferred to do the following. In the present example (see Figures 1, 2, and 3 below), there were power planes 'higher' in the PWB stack that required other solutions shown below. For the DC power distribution layers, it is critical to maintain as much Cu within the plane as possible to reduce voltage drop and I^2R heating of the assembly. Using circular anti-pads on the power planes and back-drilling the vias to minimize coupling optimizes both the high-speed differential signals and the power distribution in these regions.

    In summary, this invention relates to printed wiring board designs where the anti-pad within power or reference plane is tailored to the performance requirements of the signal traveling within a PTH or pair of PTH's, the plane adjacent to the PTH's, and the elevation of the plane within the PWB stack to optimize signal-to-signal crosstalk, power plane-to-signal crosstalk, wireability of...