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Enhanced Reliability Printed Circuit Boards Utilizing A Negative CTE Filler In The PTHs

IP.com Disclosure Number: IPCOM000238075D
Publication Date: 2014-Jul-31
Document File: 5 page(s) / 84K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a material and method to mitigate plated-through hole (PTH) cracks in printed circuit boards by use of a negative coefficient of thermal expansion (CTE) material.

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Enhanced Reliability Printed Circuit Boards Utilizing A Negative CTE Filler In The PTHs

The following disclosure solves laminate crack issues related to thermal cycling. During the qualification of thick multilayer boards, several cracked vias have been observed. Reliability testing of these boards involves subjecting them to a current-induced thermal cycling (CITC) stress test to gauge the propensity for plated-through hole (PTH) cracking leading to electrical opens. As current is driven into the PTH, resistive heating causes the temperature within the PTH to rise, simulating a solder cycle. Due to the coefficient of thermal expansion (CTE) mismatch between the laminate material and the copper in the PTH, tensile stress results in the copper (the laminate expands to a greater extent than the Cu). If there are micro cracks in the laminate, stress concentration points in the plating, or some other latent defect, CITC testing will result in barrel cracks at relatively low CITC cycles. Since it is next to impossible to match the CTE between the laminate and the Cu plating in the PTH, considerable attention is focused on eliminating micro cracks, latent plating defects, or stress risers in the board assembly. Unfortunately, oftentimes these actions are insufficient to render the PCB robust enough to pass the minimum CITC required for board qualification. Therefore, a need exists to offset the CTE mismatch between the laminate and plated copper. Currently, no known solution exists except to compromise board construction with relatively low layers of power planes and apply very stringent material control. The core idea of this invention is the application of a negative CTE material into the PTH which reduces the stress concentration on the laminate. The negative CTE material could be tailored to be used for boards of various cross-sections.

    A finite element model was constructed for a typical multilayer board to study this technique. The via is 10 mil in diameter and plated with 1 mil of Cu. The material sets used in the model were obtained directly from the supplier. This model incorporates orthotropic behavior of the material set to incorporate difference in spacial variation. The model was cooled from 210C to 25C, and strain generated in the cross-section was evaluated. This analysis is shown in Figures 1 through 2 below. The results indicate that by carefully selecting the negative CTE material for filling the via, cracks can be...