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A Method for Using a Germanium Tin (GeSn) Release Layer for Germanium Nanowire Suspension

IP.com Disclosure Number: IPCOM000238112D
Publication Date: 2014-Aug-01
Document File: 2 page(s) / 63K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is disclosed for using a Germanium Tin (GeSn) release layer for Germanium nanowire suspension.

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A Method for Using a Germanium Tin ( ((GeSn

GeSn) )

Release Layer for Germanium

Release Layer for Germanium

Nanowire Suspension
For nanowire Complementary Metal Oxide Semiconductor (CMOS) technologies, a critical step in device formation is the suspension. In process flows using Silicon (Si) n Field Effect Transistors (NFETs) and Silicon Germanium (SiGe) or Germanium (Ge) PFETs, a simultaneous release is preferred.

Disclosed is a method for using a Germanium Tin (GeSn) release layer for Ge nanowire suspension. The method utilizes a lattice matched GeSn as a release layer , wherein the GeSn is selectively etched.

Initially, one of an epitaxial (epi) Si and a GeSn stack wafer is grown on the substrate as shown in fig. 1.

Figure 1

Fig. 2 illustrates the next step of patterning a Hard Mask (HM). The blue layer represents the Silicon Dioxide (SiO2) or Silicon Nitride (SiN).

Figure 2

Thereafter, a high content SiGe is deposited on the substrate as shown in fig . 3. The green layer represents the high content SiGe.

Figure 3

Fig. 4 illustrates the subsequent step of condensing the deposited high content SiGe .

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Figure 4

Fig. 5 illustrates the next step of removing or stripping the HM from the substrate .

Figure 5

As shown in fig. 5, the left half of the figure represents an NFET region and the right half of the substrate represents a PFET region .

Thus, the method provides an efficient way of using a Germanium Tin (GeSn) release layer for Germanium nanowire...