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Browse Prior Art Database

Scan Chain Internal Chip Probe

IP.com Disclosure Number: IPCOM000238138D
Publication Date: 2014-Aug-05
Document File: 4 page(s) / 61K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that allows any flop input to be probed during the normal functioning of the chip in hardware debug. The novel contribution is a circuit and method to probe any flop input on the chip via the scan path.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 4

Scan Chain Internal Chip Probe

Debugging problems from internal nodes of a design during initial bring-up can be a daunting task with no ability to probe internal nodes during normal functioning of the chip.

A method is needed to allow any flop input to be probed during the normal functioning of the chip in hardware debug.

The novel contribution is a circuit and method to probe any flop input on the chip via the scan path. For this function, an independent scan path is created. One benefit of this path is that the probe technique works during functional mode and the probe point can be changed during functional mode. Another advantage is that, during inactive probing, during functional mode, the test scan path logic has reduced power.

The circuit and method include a grid control structure that allows the observation of any scan-able point with minimal wire overhead and removes the control flop of the existing probe test scan chain structure. With this, the AND/OR is smaller than the known flop and controls are provided by the grid.

Figure 1: Overview

• Scan connections can be utilized during functional operation
• Lower power as scan paths not wiggling due to functional operation

Figure 2: Scan

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Page 02 of 4

As shown in Figure 3, there are two registers at each intersection: one on the vertical scan chain and one on the horizontal scan chain. By controlling Scan-in's, the user can select any one intersection and observe the behavior of these two registers in real time.

Figure 3: Intersections

Any re...