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Complementary Metal-oxide Semiconductor (CMOS) Fin-shaped Field Effect Transistor (FinFET) with High Germanium (Ge) Content and Method for Fabricating the CMOS FinFET

IP.com Disclosure Number: IPCOM000238188D
Publication Date: 2014-Aug-07
Document File: 5 page(s) / 104K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a Complementary Metal-oxide Semiconductor (CMOS) Fin-shaped Field Effect Transistor (FinFET) with high Germanium (Ge) content and a method for fabricating the CMOS FinFET. The CMOS FinFET consists of Silicon-Germanium (SiGe) for a p-Channel Field-effect transistor (pFET) and Silicon (Si) for an n-Channel Field-effect transistor (nFET).

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Complementary Metal-oxide Semiconductor (CMOS) Fin-shaped Field Effect Transistor (FinFET) with High Germanium (Ge) Content and Method for Fabricating the CMOS FinFET

Silicon-germanium (SiGe) for a p-Channel Field-effect transistor (pFET) and Silicon (Si) for an n-Channel Field-effect transistor (nFET) in Fin-shaped Field Effect Transistor (FinFET) architecture are utilized mostly for a 10nm node and beyond. While fin condensation has been proposed for creating high Germanium (Ge) content fins, no experimental data exists to have sub 8nm fins which are required for electrostatics integrity. This is due to the fact that fins lift off during the oxide removal process which etches the buried Silicon dioxide (SiO2). As a result, creative solutions are required for a manufacturable process.

Disclosed is a Complementary Metal-oxide Semiconductor (CMOS) FinFET with high Ge content and a method for fabricating the CMOS FinFET. The CMOS FinFET consists of SiGe for a pFET and Si for an nFET.

In one implementation, the method for fabricating the CMOS FinFET with high Ge begins with fabricating a starting substrate. The starting substrate can be formed by a bond and etch back technique to form Si on Hafnium Oxide (HfO2) on Silicon dioxide (SiO2) as illustrated in FIG. 1.

Figure 1

Thereafter, as illustrated in FIG. 2, a mask is formed over a Shallow Trench Isolation (STI) recess using at least one of an oxide, nitride and a combination of both oxide and nitride.

1


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Figure 2

Subsequently, an epitaxial growth of SiGe is created on the pFET structure as illustrated in FIG. 3, wherein the % x varies between 10% and 30%.

Figure 3

Thereafter, a first condensation of Ge is performed to achieve uniform Ge content SiGe in the pFET region as shown in FIG. 4. Here, the % y varies from 10% t...