SiGe fin placement on silicon substrate by eliminating pre-epitaxial trench corner rounding
Publication Date: 2014-Aug-07
The IP.com Prior Art Database
Disclosed are a method and structure to overcome the problem of Silicon Germanium (SiGe) epitaxy (epi) trench corner rounding.
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SiGe fin placement on silicon substrate by eliminating pre -epitaxial trench corner rounding
The Silicon Germanium (SiGe) positive Field Effect Transistor (pFET) has been touted for 10nm finFET node and beyond. However, a Complimentary Metal-Oxide Semiconductor (CMOS) needs a Silicon (Si) negative Field Effect Transistor (nFET) and a SiGe pFET. SiGe fins are formed by forming a trench in a Si substrate first and then epitaxially growing SiGe in the trench. Due to practical issues such as trench Reactive Ion Etching (RIE) and epitaxial prebake, the trench corners are rounded, creating the problem that SiGe fins at the end of trench are shallower than those away from trench edges, rendering the edge SiGe fins unusable and increasing the requirement of nFET/pFET spacing.
The novel contribution is a method and structure to overcome the problem of SiGe epitaxy (epi) trench corner rounding.
The components and process for implementing the solution follow.
1. Start with a semiconductor substrate (e.g., bulk Si wafer)
2. Form a hardmask (e.g., silicon nitride)
3. Pattern to form a trench (trench corner is rounded due to RIE)
Figure 1: Steps 1-3
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4. Thermal oxidation (nitride spacer blocks oxidation from trench sidewall, a bird's beak is formed under the nitride spacer (see BOTS data as reference)
Figure 2: Step 4
5. Strip oxide 6. Strip nitride spacer (the nitride hardmask may be thinned, but it was much thicker than the spacer to start with, so this is not...