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Stacked Nanowire FET for Hybrid Channel FETs with no Topography

IP.com Disclosure Number: IPCOM000238225D
Publication Date: 2014-Aug-11
Document File: 5 page(s) / 138K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for the suspension of two different stacked channel materials that will have the same nanowire heights for negative and positive Field Effect Transistors (nFET and pFET).

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Stacked Nanowire FET for Hybrid Channel FETs with no Topography

A key issue in silicon nanowire Field Effect Transistors (FETs) is the wire suspension.

Additionally, with the interest stacked as well in multichannel devices (i.e. Silicon (Si) for negative FET (nFET) and Silicon Germanium/Germanium (SiGe/Ge) for positive FET (pFET)), this process becomes more involved and can lead to alternating topography between the n-wires and p-wires.

The novel contribution is a method to suspend two different stacked channel materials that have the same nanowire heights for NFET and PFET . The method uses direct

wafer bonding to form strained Si on relaxed Si substrate . For pFETs and low-leakage nFETs, the strained layer and dislocation layers are etched and relaxed Si is grown back.

The following figures represent the components and process for implementing the new method.

Figure 1: Dope the top silicon layer of a Silicon on Insulator (SOI) substrate with high arsenic (As) doping

Figure 2: Grow a thin carbon doped silicon layer into the Si:As ( [C] = 0.5 - 1.5%)

Figure 3: Selectively grow Si and SiGe (thickness = final nanowire thickness)

Figure 4: Grow a thin (1-2 nm) carbon doped silicon layer into the structure ([C] = 0.5 -
1.5%). This avoids As diffusion into channel material .

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Figure 5: Grow a highly As-doped silicon layer into the Silicon:Carbon (Si:C) layer

Figure 6: Repeat the stack n-times, as desired

Figure 7: Form Fins

Figure 8: Side view onto Fin...