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A High Gain and Low Power Clock Amplifier with Triode-Region Operation

IP.com Disclosure Number: IPCOM000238271D
Publication Date: 2014-Aug-13
Document File: 5 page(s) / 537K

Publishing Venue

The IP.com Prior Art Database

Abstract

A high gain and low power clock amplifier with triode-region operation is disclosed.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 60% of the total text.

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A High Gain and Low Power Clock Amplifier with Triode-Region Operation

Disclosed is a high gain and low power clock amplifier with triode-region operation. Here, a low common mode input is used for the clock amplifier to operate in the triode region in certain scenarios. The first stage of the clock amplifier is used for maximum gain and the second stage for maximum swing.

The clock amplifier with the low common mode input is utilized for removing peaking level shifter without any insertion loss. In a scenario, a high gain/swing amplifier is utilized for low power consumption.

Fig. 1(a) and Fig. 1(b) illustrate circuits used for the clock amplifier.

Typically the first stage of the clock amplifier takes a high common mode input voltage from a level shifter to ensure saturation of all transistors. Doing so prohibits the use of a cascode stage due to limited voltage headroom. In a technology dominated by not perfect output impedance, a cascode stage is needed to improve the gain of the amplifier. In the proposed topology, as shown in fig. 1(a), the level shifter is removed and the VCM is lowered to a value of 0.5 VIO. The first stage shown in fig. 1(a) is a cascode arrangement for larger gain and the second stage shown in fig 1(b) is in a regular arrangement for maximum swing. Both the first and second stages are much more aggressively biased near the triode region. Here, the cascode arrangement, input and mirror devices operate in the triode region in certain sce...