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Slab-type Nanowire FET Structure (SOI & Bulk) to enlarge effective channel width without short-channel degradation

IP.com Disclosure Number: IPCOM000238286D
Publication Date: 2014-Aug-14
Document File: 2 page(s) / 77K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a slab-type nanowire Field Effect Transistor (FET) structure designed to enlarge Weff at a given footprint (FP), which leads to a better Ieff-Ceff trade-off performance.

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Slab-type Nanowire FET Structure (SOI & Bulk) to enlarge effective channel width without short-channel degradation

Conventional nanowire structure engineering shows a loss of effective device channel
(i.e. reduced Fin effect) and increased capacitance, which has a significant impact on nanowire (NW) performance. (Figure 1)

Figure 1: Conventional Nanowire Structures

The electrostatic benefit of nanowire is clear.

The solution is a slab-type nanowire Field Effect Transistor (FET) structure designed to enlarge Weff at a given footprint (FP), which leads to a better Ieff-Ceff trade-off performance. The electrostatics of the wire are controlled by layer thickness, not patterning. A wider wire is immune to Dfin variation. Dielectric suspension resolves parasitic cap issue (i.e. approximately 8-10% Ceff benefit). The design introduces one additional spacer module, and assumes that an acceptable gate stack solution can be identified.

Figure 2: Slab-type Nanowire FET to enlarge effective channel width without short-channel degradation

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Figure 3: Weff Increase by Slab-type NW

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