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Placement Aware Sequential Cloning

IP.com Disclosure Number: IPCOM000238344D
Publication Date: 2014-Aug-19
Document File: 13 page(s) / 3M

Publishing Venue

The IP.com Prior Art Database

Abstract

In today’s SOC’s at lower technology nodes, the design sizes are increasing, making the placement of modules or flops placed far apart with each other. Also with decrease in Gate Length, the interconnect delay starts to dominate the gate delay constraining the max frequency of operation. For a multi-fanout path, the physical distances pose further limitations on the max frequency of the design. These multi-fanout paths are not just limited by max distance between source and sink flops but more so by max distance between the spread out flops. This paper presents a way to fix the timing issues for a multi-fanout based design with talking Flops placed far apart.

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Placement Aware Sequential Cloning

Problem Description and Motivation for Improvement

In today’s SOC’s at lower technology nodes, the design sizes are increasing, making the placement of modules or flops placed far apart with each other. Also with decrease in Gate Length, the interconnect delay starts to dominate the gate delay constraining the max frequency of operation. For a multi-fanout path, the physical distances pose further limitations on the max frequency of the design. These multi-fanout paths are not just limited by max distance between source and sink flops but more so by max distance between the spread out flops. This paper presents a way to fix the timing issues for a multi-fanout based design with talking Flops placed far apart.

Fig. 1 shows the placement of a multi-fanout design with the source flop (Green Color) placed at the centre and the sinks (Blue Color) are spread throughout the chip with the target frequency required to meet is “F MHz”.

Fig. 1: Design Placement

The Fig. 2 analyzes the timing feasibility of the design. Sinks placed at a distance of “X um” meets a frequency of “F MHz”, while the sinks placed at a distance of “X+∂1 um” meets the frequency of “F-∆1 MHz” and the sinks placed at a distance of “X+∂1+∂2 um” meets the frequency of “F-∆1-∆2 MHz”.

Fig. 2: Timing Feasibility Analysis

Proposed Solution

We propose grouping the sink flops based on actual design placement and creating the source flops clones for each group, thereby reducing the Max Distance between sink flops in each group. This reduction in Max Distance enables increase in Frequency.

Important steps of our innovation

The solution has the following steps:

•          Virtual Grouping

•          Create Placement Aware Sinks Grouping

•          Cloning

•          Datapath parsing & topological sorting of combinational cells

•          Combinational cloning & connectivity

•          Sequential Cloning & connectivity

•          Incremental Placement & Optimization using existing EDA solution

Example

Consider the design scenario shown in Fig. 3 with source flop (0) connected to 8 sink flops (1-8) via data logic cloud. The max frequency is limited due to spread of sink flops and all sink flops except Flop 6 fail timing checks as sink flop 6 is nearest to the source flop (0).

Fig. 3

Design Example Solution

Now with the proposed solution, the Design is virtually divided into groups based on the Sink Flops placement.  Figure 4 shows Four (4) physical regions (in different Color) based on Sinks Flop Placement.

In this the number of regions/clones is computed based on Required Frequency.

Fig. 4

Fig. 5

Figure 5 shows the Sequential Cloning sequence of the Sink Flops as C1, C2, C3 and C4 for each region Region1, Region2, Region3 and Region4. After the sequential cloning,...