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High Frequency Delay Locked Loop Start-Up Circuit

IP.com Disclosure Number: IPCOM000238345D
Publication Date: 2014-Aug-19
Document File: 7 page(s) / 123K

Publishing Venue

The IP.com Prior Art Database

Abstract

A simple and reliable GHz frequency input, higher numbers of phases output delay locked loop (DLL) start-up circuit is proposed. To start and lock the DLL loop, the last phase output should come properly i.e., none of it’s cycle should be missing. So, Vring (supply voltage of delay ring) should be at proper voltage to provide proper last phase out (none of it’s cycles should be missing). A comparator and logic circuit has been used to provide proper last phase output (none of it’s cycles should be missing) and protects the voltage controlled delay line transistors to go above specified voltage limit. This architecture is able to start DLL loop lock operation at any PVT.

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High Frequency Delay Locked Loop Start-Up Circuit

Abstract

A simple and reliable GHz frequency input, higher numbers of phases output delay locked loop (DLL) start-up circuit is proposed. To start and lock the DLL loop, the last phase output should come properly i.e., none of it’s cycle should be missing. So, Vring (supply voltage of delay ring) should be at proper voltage to provide proper last phase out (none of it’s cycles should be missing). A comparator and logic circuit has been used to provide proper last phase output (none of it’s cycles should be missing) and protects the voltage controlled delay line transistors to go above specified voltage limit. This architecture is able to start DLL loop lock operation at any PVT.

1.    Introduction

The accuracy of generated clock from DLL output phases would be better for higher numbers of DLL output phases. Higher the number of DLL output phases, lesser is the delay requirement between two consecutive phases. At GHz input frequency, the delay requirement between two consecutive phases would be even lesser.

DLL loop works at input frequency. Unlike PLL, in DLL there is no integration of phase (to generate frequency). So to lock DLL loop, the last phase output should come properly (none of it’s cycle should be missing). So, vring (supply voltage of delay ring) should be at proper voltage to provide proper last phase (none of it’s cycle should be missing). 

     Currently used DLL startup circuits are based on:

•           Initial charging of loop filter

•           Using phase transition method

                                                                                            In initial loop filter charging method, the loop filter voltage is charged with some reference voltage, with no direct control over DLL ring supply voltage (vring). For very low delay requirement between two consecutive phases of DLL output, the delay cells should be made of core devices. So, if loop filter control voltage is charged with some reference voltage, such that vring voltage is lower than expected, then DLL is not able to provide last phase properly (some cycles of last phase could be missing) and DLL loop will not be able to work properly. So, DLL will never lock.

Figure 1 below shows the simulation result when DLL loop start with lower vctrl/vring voltage. Figure 1 contains signals pfd_ref (DLL input clock), pfd_fb (DLL last phase output), pfd_ena (signal to enable DLL loop), UP/DN (charge pump output), vctrl (DLL loop control voltage) and vring (voltage controlled delay line supply voltage). The last phase output (pfd_fb) is not coming properly (some cycles are present and some cycle are missing due to lower vring voltage). So DLL loop is not able to operate properly and DLL will not lock.

Figure 1: Simulation result when DLL loop start with lower vctrl/vring voltage

Also if loop filter control v...