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A Semiconductor Integrated Circuit Repackaging Method for Failure Analysis

IP.com Disclosure Number: IPCOM000238347D
Publication Date: 2014-Aug-19
Document File: 4 page(s) / 993K

Publishing Venue

The IP.com Prior Art Database

Abstract

In more and more integrated circuit (IC) level failure analysis (FA), we need to change the original package to a FA friendly package to meet the requirements of various front side and backside FA technologies. In this paper we introduce a repackaging method. The process includes precise mechanical polishing to expose die bottom and backside of the copper trace (or inner lead), upside down attachment to a prepared cavity package and aluminum wedge bonding on the backside of copper trace(or lead) for electrical connection. It is capable of handling most package types, no matter the original wire type or bonding pad design.

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1.       Title:  A Semiconductor Integrated Circuit Repackaging Method for Failure Analysis

2.       Abstract

In more and more integrated circuit (IC) level failure analysis (FA), we need to change the original package to a FA friendly package to meet the requirements of various front side and backside FA technologies. In this paper we introduce a repackaging method. The process includes precise mechanical polishing to expose die bottom and backside of the copper trace (or inner lead), upside down attachment to a prepared cavity package and aluminum wedge bonding on the backside of copper trace(or lead) for electrical connection. It is capable of handling most package types, no matter the original wire type or bonding pad design.

3.       Background

IC level FA includes various of non-destructive technologies, such as Light Emission Microscopy (LEM), Infra Red Optical Beam Induced Resistance Change (IR-OBIRCH), Soft Defect Localization (SDL), laser voltage probe(LVP) and so on. It is to isolate the failed circuit, device, or to localize the physical defect directly.

LEM is to detect the photon emission from transistors, diodes or other devices, structures when the IC running a function or biased at a particular electrical condition. However, the top metal layers covered these devices, structures from front side, so that photon emission is blocked or just emerging around the top metal layers. The precise emission site cannot be observed. In the other hand, the die bottom (silicon substrate) is transparent to the photon emission which can be collected by the charge couple device (CCD) detector. Then more and more analysis (not only LEM, but also IR-OBIRCH, SDL, LVP and so on) is performed from backside.

To perform backside analysis, the die bottom (silicon substrate) is exposed, meanwhile the electrical connections maintained. But for ball grid array (BGA) package, the electrical connections are not remained after die bottom exposed. Because a part of the balls and copper traces are just under the die, as shown in Fig.1.

Figure 1: The limitation of backside FA on IC in BGA package

4.       What the solution is?

It is a solution to repackage IC for front side and backside FA. This solution covers various package types, such as quad...