Browse Prior Art Database

Method and System for Test Mode Self Checking in Hardware Description Language Based Analog Designs

IP.com Disclosure Number: IPCOM000238351D
Publication Date: 2014-Aug-19
Document File: 7 page(s) / 390K

Publishing Venue

The IP.com Prior Art Database

Abstract

The task to validate the safe state of analog input signals is becoming a big challenge because there are too many different inputs for each analog design, which are hard to track and validate especially for highly complex SoC (System on Chip) designs. Also, In certain test modes, if some analog design input signal is in wrong safe state or not in safe state, it will enable analog IP (Intellectual Property) design certain function and cause big current to the chip, which will make it impossible to test chip current in IDDQ (Integrated Circuit Quiescent Current) scan mode. Or it may generate wrong analog IP output signal which causes test pattern fail wrongly. This article introduces a method of simulating operation of a device based on a self-checking model, the model comprising several functions of the analog design and automatically reporting errors during simulation according to SoC requirements.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 37% of the total text.

Method and System for Test Mode Self Checking in Hardware Description Language Based Analog Designs

ABSTRACT

The task to validate the safe state of analog input signals is becoming a big challenge because there are too many different inputs for each analog design, which are hard to track and validate especially for highly complex SoC (System on Chip) designs. Also, In certain test modes, if some analog design input signal is in wrong safe state or not in safe state, it will enable analog IP (Intellectual Property) design certain function and cause big current to the chip, which will make it impossible to test chip current in IDDQ (Integrated Circuit Quiescent Current) scan mode. Or it may generate wrong analog IP output signal which causes test pattern fail wrongly.

This article introduces a method of simulating operation of a device based on a self-checking model, the model comprising several functions of the analog design and automatically reporting errors during simulation according to SoC requirements.

KEYWORDS

Mixed-signal, self check, analog safe mode, coverage, function mode

1.     INTRODUCTION

    There is gap between analog designer and DFT (Design for Testability) engineer, analog designer knows about the analog spec, but does not know how many test modes in different SoC and what is the difference between each test mode. The DFT engineer knows about the test spec, but he does not know the expected signal value in each analog IP. He keeps checking with each analog designer about the signals to be safe and develop his own checker.  Some important signals may not be checked correctly, no coverage related report to evaluate if the checker is enabled correctly in each test mode.

     The article introduces a method of simulating operation of a device based on a self-checking model, the model comprising several functions of the analog design and automatically reporting errors during simulation according to SoC requirements. The method mainly composes of Defining analog IP function mode with packaged expected signal value, automatically generating test configuration file that links the function modes to design, it will put analog IP in certain function mode automatically according to design states during simulation, reporting and collecting if each analog design was put into certain function mode in each SoC test mode.

      

 The self checking model could be in any hardware description language which include verilogAMS, verilogA, verilog or systemverilog.

2.     Design and Implementation

2.1     Design Flow

     A decentralized validation method is adopted by classifying IP function into several function modes ( like clock on mode, clock off mode, regulator run mode, regulator standby mode, pad input mode, pad output mode etc)  inside the analog design. Checking mechanism will check the design input output signals under certain function mode, it will report error when the compare fails.

      As Figure 1 shows, there i...