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ADC Ramp Test Method With Shift Register

IP.com Disclosure Number: IPCOM000238352D
Publication Date: 2014-Aug-19
Document File: 4 page(s) / 130K

Publishing Venue

The IP.com Prior Art Database

Abstract

This paper introduces a method of ADC Ramp Test. By adding some shift registers, the ADC conversion result can be shifted out with GPIO pin and external equipment can capture the data from the GPIO pin. Using this design, the test will neither load the CPU nor interrupt service.

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ADC Ramp Test Method With Shift Register

Abstract

This paper introduces a method of ADC Ramp Test.  By adding some shift registers, the ADC conversion result can be shifted out with GPIO pin and external equipment can capture the data from the GPIO pin.  Using this design, the test will neither load the CPU nor interrupt service.

Introduction

The ADC Ramp test typically requires a long time (MA64 10bit ramp test spend about 1.4S), so the associated cost to test and characterize it on ATE (Automatic Test Equipment) is high.

SOC cost reduction is a common goal. SOC test cost will be reduced if ADC test can be done together with other modules, such as another ADCs, PMC comparator test or SRAM/ROM BIST etc.

Although detained design information elaborated in below chapters are based on ADC shift register, it is worthy to be noted that, by simple modifications, we can port our method to those applications with any Analog test plat, such as DAC test, etc. For example, add shift register in DAC, the conversion data and DAC enable could be send to DAC automatically from external equipment without the interaction of the core.

Design and Implementation

The method introduced in this paper has four important tightly coupled components as illustrated in Figure 1.

1.      Add N+1 bits shift register.

N:   n bit analog to digital converter

 1:  one parity check bit

2.      Add one register bit (ADC_TSTEN) to enable the new test mechanism.

The (n+1) bits shifter could be enabled and GPIOs could output value of ADC_DOUT, SHIFT_CLK and ADC_COCO

3.      Add one bit shifter plus the output logic of ADC_DOUT and SHIFT_CLK

Figure 1 Test System Diagram

N+1 bits shift register just use the ADC conversion clock, the ADC Conversion Result Register shift the N bits data to shift register, when ADC conversion is done and ADC_COCO bit is set, the shift register will latch the current data and ADC_COCO and add one parity bit automatically, the shift register will sent out the data...