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Cell Design for MLC Capability Using Thermoelectrics

IP.com Disclosure Number: IPCOM000238358D
Publication Date: 2014-Aug-20
Document File: 5 page(s) / 566K

Publishing Venue

The IP.com Prior Art Database

Abstract

Phase-change memory (PCM) has emerged as one of the most promising candidates among the emerging non volatile memory technologies (RRAM, MRAM, FRAM etc) because of its speed of operation (faster than Flash memory), high throughput performance, high read/write endurance and scalability. PCM is the most mature technology and has already been demonstrated at the giga-bit density. It is based on a chalcogenide alloy, typically Ge2Sb2Te5 (GST) material, sandwiched between top and bottom electrodes. The capability to store data arises from the large resistivity contrast between the crystalline (low resistive) and the amorphous (high resistive) phase of these materials. One of the prominent features of PCM that renders it more attractive among the emerging memory technologies, is its capability to store more than 1-bit per cell, known as Multiple-Level Cell (MLC) storage. This is achieved by using intermediate resistance states for storing information, in addition to the traditional low (SET) and high (RESET) resistance levels. MLC functionality is crucial for increasing the memory capacity and thus enhancing the cost-per-GByte competitiveness of the PCM technology. Higher densities lead to more functionality, and thus more storage being demanded by big-data applications. Hence, any method helping to store more than 1-bit per cell is desirable. A key attribute of PCM which hampers its commercialization is the programming power. Traditionally, the PCM switching mechanism is attributed solely to the resistive Joule heating generated by the applied current. However, some recent studies [1-2] reveal that other thermoelectric phenomena also play a significant role in the switching dynamics of PCM cells. The coupled transport of heat and electric current can greatly impact the thermal profile within the cell and hence the performance of PCM devices as such. It has been reported that the additional heat generated from thermoelectric effects at the electrode interface yields a reduction in programming current during the reset operation by 14%. Also, unlike the joule heating, this additionally generated heat is dependent on the bias polarity. Hence, the thermoelectrics are known to affect the operating dynamics of the cell according to the applied polarity (either positive or negative). Thus the thermoelectrics impacts the efficiency of the cell based on the polarity of the programming voltage. In this article, disclosed is an idea to efficiently pack double the resistive states possible in the conventional confined cell architecture just by programming with opposite polarity conditions. A detailed FEM analysis using COMSOL was performed on the proposed cell architecture to validate its performance.

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Cell Design for MLC Capability Using Thermoelectrics

Prior art: 1) Surfactant layer
In the recent times, researchers have come up with up some innovative solutions in order to combat the drift phenomena, such as extracting drift resilient cell state metrics, modification of the cell geometry etc, One such approach to improve the drift performance is by adding metallic surfactant layer to stabilize the high resistance state drift in MLC PCM [3].

    By using a metallic surfactant layer of appropriate resistivity (typically lower than the amorphous PCM resistance), the electrical properties of the RESET state can be completely decoupled from that of the drift prone amorphous phase change material, thereby suppressing the effects of time- and temperature-dependent resistance drift and noise.

Fig. 1. (a) TEM image of a confined PCM cell and cartoon of a confined PCM cell with metal nitride (MN) surfactant layer. (b) Voltage pulses are applied to WL and BL to program and read the PCM cell [3].

Fig. 2. (Median and standard deviation) Resistance vs time plot comparison (a) without and (b) with the surfactant. With the surfactant, all resistance levels are stabilized with 6x reduction in the drift coefficient. Measurement shows a good agreement with the drift model [3].

Disclosed idea - Proposed cell design:
ñam_GST > ñP1 > ñP2 > ñcry_GST P1 - High resistance P2 - Low Resistance


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Fig. 3. Disclosed idea explaining the proposed cell design. The location of the amorphous plugging region with respect to the polarity of the applied programming voltage is illustrated.

The proposed cell design is shown in the Fig. 3.

    § The disclosed idea is, to have two different projection layer with different resistivity (P1 and P2) surrounding the phase change material towards the top and the bottom electrodes in the conventional confined cell geometries.

    § For such symmetrical confined cell, based on the polarity of the applied programming voltage, the location of hotspot will be either close to the bottom electrode (positive bias) or to the top electrode (negative polarity).

    § Corresponding to the resistivity of the projection layer (P1 and P2), different RESET resistance states can be attained for the applied bias.

    Currently multiple levels are stored in a phase-change memory by applying pulses, with varying duration of trailing edges, to a memory cell with a certain polarity, so as to program the cell at various intermediate resistive states in addition to the traditional SET and RESET states. With the state of the art cell design, a change in bias polarity of the applied programming voltage will only modify the efficiency of a cell but the programmed resistive states that can be readout is not affected.

    With the cell design proposed in this disclosure, the thermoelectric effect can be used to store information in the surrounding projection layer, such that twice as much levels as in the state of the art cell design can be stored by just swi...