Method for Self Detection of Chip Position on a 3-D Chip Stack
Publication Date: 2014-Aug-21
The IP.com Prior Art Database
AbstractDisclosed is a method to identify the chip position on the stack by integrating a resistor in the path of the TSV, using the disjoint via capability and, hence, making use of the resistor divider methodology.
Page 01 of 2
Method for Self Detection of Chip Position on a 3
3-D stacked chip ID normally programmed using Fuse blowing. This process adds more manufacturing time and extra production. Also, incorrect detection of the chip position leads to yield loss. To avoid this, another method is proposed to assign the chip ID automatically using based resistor divide network method.
A novel methodology to identify the chip position on the stack can be achieved by integrating a resistor in the path of the TSV, using the disjoint via capability and, hence, making use of the resistor divider methodology. Employ a sense circuit to identify the voltage and compare against the number programmed for accurate positioning of the chip in that particular stack (see Figure 1 below). Override the data in a register for software/hardware to understand the positioning. In case of chip not being used, then software can override this register to a newer value.
33---D Chip Stack D Chip Stack
As shown in Figure 2 below:
Page 02 of 2
Chip position is self detected each time upon chip power-up.
The current through the TSV & R stack can be minimized by using a big R.
Similarly, the current through the Resistor Divider circuit and comparator shall be saved by turning off the circuits after detection.
This concept shall be implemented independent of the number of chips in the stack.
Instead of detecting voltage, current detection is possible as well.
The comparator is tuned to detect a range of v...