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Automated Reduced Netlist for Efficiency Gains

IP.com Disclosure Number: IPCOM000238383D
Publication Date: 2014-Aug-21
Document File: 2 page(s) / 41K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a method of creating a comprehensive reduced netlist model from an existing netlist independent of hierarchical boundaries.

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This is the abbreviated version, containing approximately 51% of the total text.

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Automated Reduced Netlist for Efficiency Gains

As the size and content of silicon chips continues to increase, so does the time and computational requirements needed to complete the physical design work on a chip. This invention will reduce the time and computational resource needed to finalize a physical design netlist. During the physical design processing, there can be localized issues that demand significant changes to the current state of the design. Sometimes these changes need several tool iterations to find an ideal solution. Because of current design sizes, these iterations can be very time and resource consuming. This invention is to extract and save a "reduced netlist on the fly" that is able to be loaded and iterated much faster due to its reduction in size. This reduced netlist model will still contain a high degree of placement, wiring, and timing information. There are currently means to create similar abstracts around defined units with existing timing constraints. This invention would create an abstraction independent of hierarchal boundaries based on the user's needs.

    The core idea of this invention is to create a comprehensive "reduced netlist on the fly" by selecting an area or set of timing paths (endpoints) from a fully loaded and timed design. This selected data set would then become a new netlist complete with all circuits, wires, ports (for nets that cross the boundary), and timing assertions (constraints). One would then be able to iterate on any placement/wiring/resi...