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Decoupled Soft Error Handling in Microprocessor

IP.com Disclosure Number: IPCOM000238405D
Publication Date: 2014-Aug-25
Document File: 3 page(s) / 66K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for low cost handling of soft errors in a microprocessor.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 3

Decoupled Soft Error Handling in Microprocessor

Low-voltage and process scaling increase the rate of particle-induced soft errors and threaten to produce multiple-bit errors. Current processes for detection and correction of all registers are costly to implement. A method is needed for efficient detection and recovery against bit-flips in microprocessor storage.

The novel solution is a method for low cost handling of soft errors in a microprocessor . This method includes detecting a soft error, indicating a register has a soft error, flushing a microprocessor pipeline, identifying the location of the error correcting code, recovering architectural states through the said code, and resuming operation.

This solution is more efficient than current approaches because it reduces cycle time on normal access timing paths and does not perform corrections when soft errors are not detected.

The method comprises Compute Error Correction Code (ECC) and parity upon loading entries into storage. When reading storage, parity is recomputed and compared to the initially generated parity. If a parity mismatch is found, then the system flushes the microprocessor and scrubs the storage using the generated ECC code . The microprocessor then attempts to read the storage again (i.e. retries).

Figure 1: System diagram

This method can be applied to the following use cases :


● Lane Instruction buffer or core instruction cache


● Graphics Processing Unit (GPU) texture or Read-Only memory


● Single Instruction/Multiple Data (SIMD)/Very Long Instruction Word (VLIW) or scalar register file in in-order/out-order microprocessors

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In a preferred embodiment, selected registers have parity detection (preferably all) and only selected registers have duplicates in the hardware register file. (Figure 2)

Figure 2: Hardware Flow chart (Preferred Embodiment)

Example Embodiment #1: Instruction Buffer


For the 20KB (512 entries * 42 bytes) Lane Instruction Buffer (LIB), the method decouples detection and correction to leverage the unique properties of LIB : 1) most of its acc...