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3D TSV DECAP Method

IP.com Disclosure Number: IPCOM000238436D
Publication Date: 2014-Aug-26
Document File: 1 page(s) / 50K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed to design 3D products with placement of Deep Trench Capacitor (DTCAP) in three dimensional (3D) Through Silicon Via (TSV) keepout area. This method and system utilizes space in the circuit keepout area for DECAP and for Electrostatic Discharge (ESD) protection.

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3D TSV DECAP Method

Placement of Deep Trench Capacitor (DTCAP) in three-dimensional (3D) Through Silicon Via (TSV) keepout areas have been shown to be effective as Electrostatic Discharge (ESD) protection. Similar DTCAPs can be used as noise mitigation. Placement of these structures in the keepout area in 3D products allows use of space for active circuits that would otherwise be unused.

The flow chart below shows how to apply use of this structure in the design of 3D products. A DECAP library, called a "TSV DECAP Library", is created to fit into the 3D keepout area in 3D products. The library is composed of DECAPS with different purposes (e.g., Power Ground Cap, Signal Decoupling, Decap Voltage Converter, etc.). A variety of different sizes is created for each DECAP purpose.

During product design, the signal DECAP needs are identified for the module and DECAPs are selected from the TSV DECAP Library to satisfy the design needs. The identified DECAPs are integrated into Product Chip and Module design.

Use of this technique allows previously unused areas in the keepout area to be used for both noise mitigation and ESD requirements, thus minimizing use of active area in the chip or application of discrete capacitors in the module and improving product cost.

Figure: Applying this structure in the design of 3D products

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